Test structures for evaluating a fabrication of a die or a wafer

• US 8,344,745 B2
• Filed: 08/31/2006
• Issued: 01/01/2013
• Est. Priority Date: 08/25/2003
• Status: Active Grant

• Current Assignee: Tel Venture Capital, Inc. (Tokyo Electron Limited)
• Original Assignee: Tau-Metrix, Inc.
• Inventors: Aghababazadeh, Majid, Estabil, Jose J., Pakdaman, Nader, Steinbrueck, Gary L., Vickers, James S.
• Primary Examiner(s): NGUYEN, VINH P
• Application Number:
  US11/469,305
• Publication Number:
  US 20070004063A1
• Time in Patent Office: 2,315 Days
• Field of Search: None
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/3025 Wireless interface with the DUT
• CPC Class Codes: G01R 31/31707 Test strategies methods for generation of test sequences G01R31/318371
• CPC Class Codes: G01R 31/31718 Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis mechanical aspects G01R31/2808, G01R31/2851
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The fabrication of the wafer may be analyzed starting from when the wafer is in a partially fabricated state. The value of a specified performance parameter may be determined at a plurality of test structures located on an active area of a die of the wafer. The specified performance parameter is known to be indicative of a particular fabrication process in the fabrication. Evaluation information may then be obtained based on a variance of the value of the performance parameter at the plurality of locations. This may be done without affecting a usability of a chip that is created from the die. The evaluation information may be used to evaluate how one or more processes that include the particular fabrication process that was indicated by the performance parameter value was performed.

Claims

1. A test structure for evaluating a fabrication of a wafer, the test structure comprising:

a combination of device and interconnect elements that are provided on an active region of a die on the wafer prior to the fabrication of the wafer being completed, the combination of device and interconnect elements including one or more circuits that are activatable to produce an output corresponding to measurable electrical and/or optical characteristics;

wherein the combination includes a power receiving element that is configured to receive activation energy sufficient to cause the output on a contactless medium, so that the activation energy is received without affecting a usability of the die or wafer;

wherein the one or more circuits are structured to generate an output that is measurably responsive to a device parameter or a process variation in a specific fabrication step.

2. The test structure of claim 1, wherein the one or more circuits are configured to generate the output to be measurably responsive to a presence of a physical or electrical characteristic that results from the specific fabrication step.

3. The test structure of claim 1, wherein the output corresponds to one or more of (i) an output signal, (ii) photon emission, (iii) electron emissions, and (iv) an electrical effect.

4. The test structure of claim 1, wherein the one or more circuits are activatable by application of an energy beam onto the power receiving element, and wherein the output includes photons produced from a switch element in the one or more circuits.

5. The test structure of claim 1, wherein the one or more circuits are activatable by application of an energy beam onto the power receiving element, and wherein the output includes at least one of an electrostatic, electromagnetic or inductive signal.

6. The test structure of claim 1, wherein the one or more circuits includes a plurality of interconnected inverters.

7. The test structure of claim 6, wherein the one or more circuits includes one or more CMOS inverters.

8. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to a relative value of a transistor gate length and a transistor gate width.

9. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to interconnect resistance amongst the plurality of transistors and the interconnect elements.

10. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to interconnect capacitance amongst the plurality of transistors and interconnect elements.

11. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to gate capacitance amongst the plurality of transistors and interconnect elements.

12. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably measurably responsive for determining a performance parameter that is related to an influence of gate film stack on one or more gates of the plurality of transistors.

13. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to an influence of a gate source drain extension implant.

14. The test structure of claim 1, wherein the one or more circuits includes a plurality of transistors, and wherein the output is measurably responsive for determining a performance parameter that is related to an influence of contact resistance amongst the plurality of transistors and the interconnect elements.

15. The test structure of claim 1, wherein the one or more circuits are activatable by a stimulating signal.

16. The test structure of claim 1, wherein the one or more circuits are activatable by a modulating signal.