RFID tags with synchronous power rectifier

• US 8,344,857 B1
• Filed: 11/30/2011
• Issued: 01/01/2013
• Est. Priority Date: 03/07/2007
• Status: Active Grant

• Current Assignee: Impinj, Inc.
• Original Assignee: Impinj, Inc.
• Inventors: Oliver, Ronald A., Peach, Charles J. T., Hyde, John D.
• Primary Examiner(s): Bugg, George
• Assistant Examiner(s): OBINIYI, PAULSON IDOWU
• Application Number:
  US13/307,098
• Time in Patent Office: 398 Days
• Field of Search: 340 101- 106, 3405721-5729, 235375-385, 327/156, 327/157, 327/536
• US Class Current: 340/10.1
• CPC Class Codes: G06K 19/0701 at least one of the integrated circuit chips comprising an arrangement for power management
• CPC Class Codes: G06K 19/0713 the arrangement including a power charge pump
• CPC Class Codes: H04Q 2213/1308 Power supply
• CPC Class Codes: H04Q 2213/13095 PIN / Access code, authentication

Abstract

The present disclosure provides a power rectifier for a Radio Frequency Identification tag circuit. The rectifier is constructed from a pair of complementary MOS transistors. Gates of the transistors have predetermined voltages applied to them. The applied voltages bias the transistors to near their active operating region. During the same time additional control signals are applied to the gates of the transistors, the control signals are synchronous, but out of phase, with each other.

Claims

1. A rectifier for a Radio Frequency Identification tag, comprising:

a first antenna input,

a second antenna input,

first, second, third, and fourth capacitors,

a first transistor including an input terminal, an output terminal, and a gate, and

a second transistor of a type complementary to the first transistor and including

an input terminal, an output terminal, and a gate, wherein,

the input terminal of the first transistor is coupled to a beginning node,

the output terminal of the first transistor is coupled to an averaging node,

the input terminal of the second transistor is coupled to the averaging node,

the output terminal of the second transistor is coupled to an ending node,

the first antenna input is coupled to the gate of the first transistor and to the ending node,

the second antenna input is coupled to the gate of the second transistor and to the beginning node,

the first antenna input is coupled to the ending node via the first capacitor,

the second antenna input is coupled to the beginning node via the second capacitor,

the first antenna input is coupled to the gate of the first transistor via the third capacitor, and

the second antenna input is coupled to the gate of the second transistor via the fourth capacitor.

2. The rectifier of claim 1, further comprising an averaging-node capacitor coupling the averaging node to at least one of a ground, a substrate, and another averaging node.

3. The rectifier of claim 1, further comprising a third transistor including an input terminal, an output terminal, and a gate, wherein the input terminal of the third transistor is coupled to a ground node, the output terminal of the third transistor is coupled to the beginning node, and the gate of the third transistor is coupled to the first antenna input.

4. The rectifier of claim 3, wherein the second and third transistors are of the same type.

5. The rectifier of claim 3, further comprising a fifth capacitor coupling the first antenna input to the gate of the third transistor.

6. A rectifier for a Radio Frequency Identification tag, comprising:

a first antenna input,

a second antenna input,

first, second, third, fourth, and fifth capacitors,

a first transistor including an input terminal, an output terminal, and a gate,

a second transistor of a complementary type to the first transistor and including

an input terminal, an output terminal, and a gate, and

a third transistor including an input terminal, an output terminal, and a gate, wherein;

the input terminal of the first transistor is coupled to a beginning node,

the output terminal of the first transistor is coupled to an averaging node,

the input terminal of the second transistor is coupled to the averaging node,

the output terminal of the second transistor is coupled to an ending node,

the input terminal of the third transistor is coupled to a ground node,

the output terminal of the third transistor is coupled to the beginning node,

the first antenna input is coupled to the gate of the first transistor, the gate of the third transistor, and the ending node,

the second antenna input is coupled to the gate of the second transistor and the beginning node,

the first antenna input is coupled to the ending node via the first capacitor,

the second antenna input is coupled to the beginning node via the second capacitor,

the first antenna input is coupled to the gate of the first transistor via the third capacitor and the gate of the third transistor via the fifth capacitor, and

the second antenna input is coupled to the gate of the second transistor via the fourth capacitor.

7. The rectifier of claim 6, further comprising:

a fourth transistor including an input terminal, an output terminal, and a gate, and

a fifth transistor of a complementary type to the fourth transistor and the first transistor, and including an input terminal, an output terminal, and a gate, wherein;

the input terminal of the fourth transistor is coupled to the ending node,

the output terminal of the fourth terminal is coupled to a second averaging node,

the input terminal of the fifth transistor is coupled to the second averaging node,

the output terminal of the fifth transistor is coupled to a second ending node,

the first antenna input is further coupled to the gate of the fifth transistor, and

the second antenna input is further coupled to the gate of the fourth transistor and the second ending node.

8. The rectifier of claim 7, further comprising a sixth capacitor coupling the second antenna input to the second ending node.

9. The rectifier of claim 8, further comprising seventh and eighth capacitors, wherein:

the first antenna input is coupled to the gate of the fifth transistor via the seventh capacitor, and

the second antenna input is coupled to the gate of the fourth transistor via the eighth capacitor.

10. The rectifier of claim 7, further comprising a second averaging node capacitor coupling the second averaging node to at least one of a ground, a substrate, and a different averaging node.

11. A Radio Frequency Identification tag, comprising:

a first antenna having a first antenna terminal and a second antenna terminal, and

a rectifier comprising;

a first antenna input coupled to the first antenna terminal,

a second antenna input coupled to the second antenna terminal,

first, second, third, fourth, and fifth capacitors,

a first transistor including an input terminal, an output terminal, and a gate,

a second transistor of a complementary type to the first transistor and including an input terminal, an output terminal, and a gate, and

a third transistor including an input terminal, an output terminal, and a gate, wherein;

the input terminal of the first transistor is coupled to a beginning node,

the output terminal of the first transistor is coupled to an averaging node,

the input terminal of the second transistor is coupled to the averaging node,

the output terminal of the second transistor is coupled to an ending node,

the input terminal of the third transistor is coupled to a ground node,

the output terminal of the third transistor is coupled to the beginning node;

the first antenna input is coupled to the gate of the first transistor,

the gate of the third transistor, and the ending node,

the second antenna input is coupled to the gate of the second transistor and the beginning node,

the first antenna input is coupled to the ending node via the first capacitor,

the second antenna input is coupled to the beginning node via the second capacitor,

the first antenna input is coupled to the gate of the first transistor via the third capacitor and the gate of the third transistor via the fifth capacitor, and

the second antenna input is coupled to the gate of the second transistor via the fourth capacitor.

12. The tag of claim 11, wherein the rectifier further comprises:

a fourth transistor including an input terminal, an output terminal, and a gate, and

a fifth transistor of a complementary type to the fourth transistor and the first transistor and including an input terminal, an output terminal, and a gate, wherein

the input terminal of the fourth transistor is coupled to the ending node,

the output terminal of the fourth transistor is coupled to a second averaging node,

the input terminal of the fifth transistor is coupled to the second averaging node,

the output terminal of the fifth transistor is coupled to a second ending node,

the first antenna input is further coupled to the gate of the fifth transistor, and

the second antenna input is further coupled to the gate of the fourth transistor and the second ending node.

13. The tag of claim 12, wherein the rectifier further comprises a sixth capacitor coupling the second antenna input to the second ending node.

14. The tag of claim 13, wherein the rectifier further comprises seventh and eighth capacitors, wherein

the first antenna input is coupled to the gate of the fifth transistor via the seventh capacitor, and

the second antenna input is coupled to the gate of the fourth transistor via the eighth capacitor.

15. The tag of claim 11, wherein the rectifier further comprises a second averaging node capacitor coupling the second averaging node to at least one of a ground, a substrate, and a different averaging node.