Semiconductor device having multi access level and access control method thereof
First Claim
1. A method of controlling access to an inner circuit in an interface circuit of a semiconductor device which includes the interface circuit and the inner circuit, the method comprising:
- providing an inputted password as an input of a hash operator;
performing a hash operation in the hash operator and outputting a first hash value;
controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide, wherein the second hash value is initially determined using a predetermined password as an input to the hash operator and is then rehashed by the hash operator a predetermined number of times; and
setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide,wherein setting an access level sets the access level with respect to the inner circuit at a highest level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide and sets the access level with respect to the inner circuit at a level corresponding to K if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide,wherein the inner circuit comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide, andwherein the access level with respect to the inner circuit comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level.
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Accused Products
Abstract
An access control method of a semiconductor device includes providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide.
15 Citations
10 Claims
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1. A method of controlling access to an inner circuit in an interface circuit of a semiconductor device which includes the interface circuit and the inner circuit, the method comprising:
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providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide, wherein the second hash value is initially determined using a predetermined password as an input to the hash operator and is then rehashed by the hash operator a predetermined number of times; and setting an access level with respect to the inner circuit according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide, wherein setting an access level sets the access level with respect to the inner circuit at a highest level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide and sets the access level with respect to the inner circuit at a level corresponding to K if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide, wherein the inner circuit comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide, and wherein the access level with respect to the inner circuit comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level. - View Dependent Claims (2, 3, 4)
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5. A semiconductor device comprising:
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an inner circuit; a hash operator performing a hash operation with respect to an input and outputting a first hash value; and a secure controller providing passwords inputted from the outside as an input of the hash operator and setting an access level with respect to the inner circuit according to a repetition number of times of the hash operation when a first hash value outputted from the hash operator and the second hash value stored in the nonvolatile memory coincide, wherein the second hash value is initially determined using a predetermined password as an input to the hash operator and is then rehashed by the hash operator a predetermined number of times, wherein the secure controller controls the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first and second hash values coincide, wherein the secure controller provides the first hash value outputted from the hash operator as an input of the hash operator repeatedly a maximum number of n (n is a positive integer) times, sets an access level with respect to the inner circuit at a highest access level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide, and sets an access level with respect to the inner circuit at a level corresponding to k if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide, wherein the inner circuit comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide, and wherein the access level with respect to the inner circuit comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level. - View Dependent Claims (6)
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7. A method of controlling access in an interface circuit of a semiconductor device which includes the interface circuit, the method comprising:
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providing an inputted password as an input of a hash operator; performing a hash operation in the hash operator and outputting a first hash value; controlling the hash operator so that the hash operation is repeatedly performed in the hash operator by providing the first hash value as an input of the hash operator when the first hash value and a second hash value stored in a nonvolatile memory do not coincide, wherein the second hash value is initially determined using a predetermined password as an input to the hash operator and is then rehashed by the hash operator a predetermined number of times; and setting an access level according to the repetition number of times of the hash operation of the hash operator when the first and second hash values coincide, wherein setting an access level sets the access level at a highest level if the repetition number of times of the hash operation of the hash operator is n when the first and second hash values coincide and sets the access level at a level corresponding to k if the repetition number of times of the hash operation of the hash operator is k (k is a positive integer smaller than n) when the first and second hash values coincide, wherein the semiconductor device comprises a memory including a plurality of memory regions and wherein setting an access level comprises setting a region which can be accessed among the plurality of memory regions of the memory according to the number of times of the hash operation of the hash operator when the first and second hash values coincide, and wherein the access level comprises a phased plurality of access levels and a high access level can access a memory region which can be accessed by a low access level. - View Dependent Claims (8, 9, 10)
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Specification