Selective floating body SRAM cell

• US 8,349,670 B2
• Filed: 03/11/2011
• Issued: 01/08/2013
• Est. Priority Date: 07/20/2009
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Chang, Josephine B., Chang, Leland, Koester, Steven J., Sleight, Jeffrey W.
• Primary Examiner(s): MENZ, LAURA MARY
• Application Number:
  US13/045,756
• Publication Number:
  US 20110171790A1
• Time in Patent Office: 669 Days
• Field of Search: 438/129, 438153-154
• US Class Current: 438/153
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]

Abstract

A memory cell has N≧6 transistors, in which two are access transistors, at least one pair [say (N−2)/2] are pull-up transistors, and at least another pair [say (N−2)/2] are pull-down transistors. The pull-up and pull-down transistors are all coupled between the two access transistors. Each of the access transistors and the pull-up transistors are the same type, p-type or n-type. Each of the pull-down transistors is the other type, p-type or n-type. The access transistors are floating body devices. The pull-down transistors are non-floating body devices. The pull-up transistors may be floating or non-floating body devices. Various specific implementations and methods of making the memory cell are also detailed.

Claims

1. A method of making a memory cell comprising:

doping a first region of a semiconductor substrate with one of an n-type or a p-type dopant and doping a second region of the semiconductor substrate with the other of an n-type or a p-type dopant;

forming over the first region a pair of access transistors that are floating body devices and at least one pair of pull-down transistors that are non-floating body devices;

forming over the second region at least one pair of pull-up transistors; and

coupling the pair of pull-down transistors and the pair of pull-up transistors between the pair of access transistors to form a memory cell,

wherein forming over the first region the pair of access transistors that are floating body devices comprises forming the body of each of the access transistors from a layer of partially depleted silicon-on-insulator, and wherein forming over the first region the at least one pair of pull-down transistors that are non-floating body devices comprises forming for each of the pull-down transistors a finFET channel comprising parallel fins spaced from one another and each fin controlled by at least one common gate.

2. The method of claim 1, wherein doping the first region of the semiconductor substrate is with a p-type dopant and doping the second region of the semiconductor substrate is with an n-type dopant.

3. The method of claim 1, wherein each of the said pull-up transistors is a floating body device.

4. The method of claim 1, wherein each of the said pull-up transistors comprises a non-floating body device.

5. The method of claim 4, wherein the memory cell comprises a static random access memory cell, and wherein coupling the pair of pull-down transistors and the pair of pull-up transistors between the pair of access transistors comprises coupling each gate of the pull-down transistors and each gate of the pull-up transistors to a channel of at least one of the access transistors.

6. The method of claim 1, wherein forming over the first region the pair of access transistors that are floating body devices comprises forming each body of the said access transistors from a first silicon layer having thickness about 50 nm or more that overlies an insulating layer,

and wherein forming over the first region the at least one pair of pull-down transistors that are non-floating body devices comprises forming the body of each of the said pull-down transistors from a second silicon layer having thickness about 25 nm or less that overlies the insulating layer.

7. The method of claim 6, wherein a combined thickness of the first silicon layer and a portion of the insulating layer that underlies the first silicon layer is equal to a combined thickness of the second silicon layer and a portion of the insulating layer underlying the second silicon layer.

8. The method of claim 1, wherein forming over the first region the at least one pair of pull-down transistors that are non-floating body devices comprises, for each of the pull-down transistors, forming at least one body tie that electrically contacts a source or a drain to a body of the pull-down transistor.

9. The method of claim 8, wherein the body tie comprises a pair of Schottky body ties that electrically contacts the body to both the source and to the drain.

10. The method of claim 8, wherein there is only one body tie for each of the said pull-down transistors, formed by masking deep implantation of one of the source or drain that is to have the body tie.

11. The method of claim 1, wherein forming over the first region the pair of access transistors that are floating body devices comprises forming a body of each of the said access transistors from a layer of partially depleted silicon over insulator, and wherein forming over the first region the at least one pair of pull-down transistors that are non-floating body devices comprises forming the body of each of the said pull-down transistors from bulk silicon having a crystalline structure.