Integrated method for high-density interconnection of electronic components through stretchable interconnects

• US 8,349,727 B2
• Filed: 04/08/2011
• Issued: 01/08/2013
• Est. Priority Date: 04/08/2010
• Status: Expired due to Fees

• Current Assignee: Liang Guo, Stephen P. Deweerth
• Original Assignee: Liang Guo, Stephen P. Deweerth
• Inventors: Guo, Liang, DeWeerth, Stephen P.
• Primary Examiner(s): CHU, CHRIS C
• Application Number:
  US13/083,111
• Publication Number:
  US 20110254171A1
• Time in Patent Office: 641 Days
• Field of Search: 438/629, 438/637, 438/639, 438/640, 438/667, 438/668, 438/672, 438/675, 438/700, 438/701, 438/713, 438/978, 257/E23.011, 257/758, 257773-776, 427/98.4, 216/20
• US Class Current: 438/637
• CPC Class Codes: A61N 1/0543 Retinal electrodes
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01074 Tungsten [W]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H05K 1/0283 : Stretchable printed circuits
• CPC Class Codes: H05K 1/185 : Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit semiconductor chips encapsulated by interconnect and support structures H01L23/5389, H01L24/00
• CPC Class Codes: H05K 2201/09509 : Blind vias, i.e. vias having one side closed
• CPC Class Codes: H05K 3/4644 : by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: H05K 3/4691 : Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers

Abstract

Stretchable multi-chip modules (SMCMs) are capable of withstanding large mechanical deformations and conforming to curved surfaces. These SMCMs may find their utilities in elastic consumer electronics such as elastic displays, skin-like electronic sensors, etc. In particular, stretchable neural implants provide improved performances as to cause less mechanical stress and thus fewer traumas to surrounding soft tissues. Such SMCMs usually comprise of various electronic components attached to or embedded in a polydimethylsiloxane (PDMS) substrate and wired through stretchable interconnects. However, reliably and compactly connecting the electronic components to PDMS-based stretchable interconnects is very challenging. This invention describes an integrated method for high-density interconnection of electronic components through stretchable interconnects in an SMCM. This invention has applications in high-density SMCMs, as well as high-density stretchable/conformable neural interfaces.

Claims

1. A method of bonding flexible interconnects to a substrate, comprising the steps of:

coating the substrate with a layer of negative photoresist;

photo-lithographically patterning the negative photoresist layer to produce tapered posts on the substrate wherein said photo-lithographically patterning involves purposely adding a gap between said negative photoresist layer surface and a photomask to modulate the UV light intensity profile by aperture diffraction;

forming a polydimethylsiloxane layer no thicker than the height of said tapered posts on said substrate wherein said polydimethylsiloxane layer is formed by spin-coating and thermal curing;

forming inclined-vias in said polydimethylsiloxane layer wherein said inclined-vias have inclined slopes and are molded by said tapered posts after removal of said tapered posts by acetone and plasma etching; and

patterning thin film interconnects on said polydimethylsiloxane layer wherein the portion of said thin film interconnect deposited on slopes and bottom of said inclined-via electrically connects to a bonding pad on said substrate.

2. The method of claim 1, wherein said flexible interconnects comprises at least one polydimethylsiloxane layer with conductive traces on top of said polydimethylsiloxane layer.

3. The method of claim 1, wherein said substrate comprises at least one bonding pad and is selected from the group comprising pre-fabricated integrated circuit chips, glass, quartz, polyimide, Kapton, Kapton printed circuit boards, FR4 printed circuit boards, parylene, polydimethylsiloxane.

4. The method of claim 1, wherein said purposely added gap is greater than 500 microns and is filled by a transparent spacer comprising an air gap, a vacuum gap, a glass, or a polymer film.

5. The method of claim 1, wherein said patterning thin film interconnects uses methods comprising lift-off metallization, wet-etching, or shadow-masking.

6. The method of claim 5, wherein said thin film interconnects are deposited using processes comprising e-beam evaporation, sputtering, physical vapor deposition, electroplating, or ion implantation.

7. The method of claim 5, wherein said thin film interconnects comprise conductive materials selected from the group comprising of gold, platinum, titanium, platinum and iridium oxide, grapheme, graphite, polypyrrole, poly(3,4-ethylenedioxythiophene).

8. The method of claim 1, further comprising:

forming a second polydimethylsiloxane layer on said first polydimethylsiloxane layer wherein said second polydimethylsiloxane layer comprises at least one inclined-via; and

patterning thin film interconnects on said second polydimethylsiloxane layer to form interconnections to conductive interconnects on said first polydimethylsiloxane layer or said substrate through said inclined-vias.

9. The method of claim 8, further comprising:

forming a third polydimethylsiloxane layer on said second polydimethylsiloxane layer wherein said third polydimethylsiloxane layer comprises at least one inclined-via; and

patterning thin film interconnects on said third polydimethylsiloxane layer to form interconnections to conductive interconnects on said second or said first polydimethylsiloxane layer or said substrate through said inclined-vias.

10. The method of claim 9, wherein said inclined-vias comprising inclined-vias through a single said polydimethylsiloxane layer, inclined-vias stacked vertically going through multiple said polydimethylsiloxane layers, and inclined-via based interconnections relayed going through multiple said polydimethylsiloxane layers.

11. A lift-off method comprising the steps of:

forming a sacrificial layer on a substrate;

forming a layer of SU-8 on said sacrificial layer, wherein said SU-8 layer is patterned by a lithography method comprising UV lithography or e-beam lithography;

removing said sacrificial layer on exposed said substrate in SU-8 windows;

depositing a conductive thin film onto exposed areas of said substrate; and

dissolving said sacrificial layer underneath said SU-8 mask to remove said SU-8 mask and excess metal film on top of said SU-8 mask.

12. The method of claim 11, wherein said sacrificial layer comprises water soluble polymers or photoresists.

13. The method of claim 11, wherein said substrate comprises polydimethylsiloxane.

14. The method of claim 11, wherein said conductive thin film comprise materials selected from the group consisting of gold, platinum, chromium, titanium, aluminum, platinum, iridium oxide, graphite, and conducting polymers.