Compensated gate MISFET and method for fabricating the same
DCFirst Claim
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1. A column III Nitride transistor comprising:
- a substrate,a set of III-N transition layers above the substrate,a III-N buffer layer above the set of transition layers,a III-N barrier layer above the buffer layer,a compensated GaN layer above the barrier layer, anda gate contact above the compensated GaN layer.
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Abstract
A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.
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Citations
12 Claims
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1. A column III Nitride transistor comprising:
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a substrate, a set of III-N transition layers above the substrate, a III-N buffer layer above the set of transition layers, a III-N barrier layer above the buffer layer, a compensated GaN layer above the barrier layer, and a gate contact above the compensated GaN layer. - View Dependent Claims (2, 3)
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4. A column III Nitride transistor comprising:
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a substrate, a set of III-N transition layers above the substrate, a III-N buffer layer above the set of transition layers, a III-N barrier layer, and a semi-insulating III-N layer above the barrier layer. - View Dependent Claims (5, 6)
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7. A column III Nitride transistor comprising:
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a substrate, a set of III-N transition layers above the substrate, a III-N buffer layer above the set of transition layers, a III-N barrier layer, a semi-insulating III-N layer above the barrier layer, and a confinement layer above the semi-insulating III-N layer. - View Dependent Claims (8, 9)
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10. A compensated gate MISFET transistor comprising:
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a III-N barrier layer beneath a gate contact, a drain contact, a source contact, and a semi-insulating III-N layer between the barrier layer and the gate contact. - View Dependent Claims (11, 12)
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Specification