Power semiconductor devices and methods of manufacture

• US 8,350,317 B2
• Filed: 12/11/2009
• Issued: 01/08/2013
• Est. Priority Date: 05/20/2003
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Kocon, Christopher B.
• Primary Examiner(s): Warren, Matthew E
• Application Number:
  US12/636,011
• Publication Number:
  US 20100084706A1
• Time in Patent Office: 1,124 Days
• Field of Search: 257328-332, 257/341, 257/E29.131, 257/E29.256, 257/E29.257, 257/E29.26
• US Class Current: 257/328
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/30655 comprising alternated and repeated etching and passivation steps, e.g. Bosch process
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68363 used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 : with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 : within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 : characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 : with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/495 : the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66348 : with a recessed gate
• CPC Class Codes: H01L 29/66734 : with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7396 : with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7802 : Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7804 : the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7805 : in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7806 : the other device being a Schottky barrier diode
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7815 : with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
• CPC Class Codes: H01L 29/7828 : without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/12032 : Schottky diode
• CPC Class Codes: H01L 2924/1301 : Thyristor
• CPC Class Codes: H01L 2924/13034 : Silicon Controlled Rectifier [SCR]
• CPC Class Codes: H01L 2924/1305 : Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H02M 3/00 : Conversion of dc power input into dc power output
• CPC Class Codes: H02M 3/33592 : having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode
• CPC Class Codes: Y02B 70/10 : Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.

Claims

1. A semiconductor device comprising:

a drift region of first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending into the drift region deeper than the well region, the active trench comprising;

dielectric material that lines sidewalls and bottom of the active trench;

a gate conductive layer disposed between the dielectric material; and

a shield electrode comprising a first conductive material formed under the gate conductive layer inside the active trench, the shield electrode being insulated from the gate conductive layer by a layer of dielectric material and insulated from the sidewalls and the bottom of the active trench by the dielectric material;

source regions having the first conductivity type and formed in the well region adjacent the active trench;

a body trench formed adjacent the well region and at least one of the source regions, the body trench being substantially filled with a second conductive material; and

a second layer having the second conductivity type, the second layer substantially surrounding the body trench and extending deeper than the well region into the drift region, the second layer having a concentration of the second conductivity type that is greater than a concentration of the second conductivity type of the well region;

wherein the second layer influences an electric field near the active trench.

2. The semiconductor device of claim 1 wherein the body trench is substantially filled with any one of metal, epitaxial material and doped polysilicon that is electrically coupled to the source regions.

3. The semiconductor device of claim 1 wherein the gate conductive layer substantially fills the active trench.

4. The semiconductor device of claim 1 wherein the body trench is deeper than the active trench.

5. A semiconductor device comprising:

a drift region of first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending into the drift region deeper than the well region, the active trench comprising;

dielectric material that lines sidewalls and bottom of the active trench;

a gate conductive layer disposed between the dielectric material;

source regions having the first conductivity type and formed in the well region adjacent the active trench;

a body trench formed adjacent the well region and at least one of the source regions, the body trench being substantially filled with a first conductive material and extending into the drift region deeper than the active trench; and

a second layer having the second conductivity type, the second layer substantially surrounding the body trench and extending deeper than the well region into the drift region, the second layer having a concentration of the second conductivity type that is greater than a concentration of the second conductivity type of the well region;

wherein the second layer influences an electric field near the active trench.

6. The semiconductor device of claim 5 wherein the active trench further includes a shield electrode made of a second conductive material formed under the gate conductive layer, the shield electrode inside the active trench being insulated from the gate conductive layer and the sidewalls and bottom of the active trench by a layer of dielectric material.

7. The semiconductor device of claim 5 wherein the body trench is substantially filled with any one of metal, epitaxial material and doped polysilicon that is electrically coupled to the source regions.

8. The semiconductor device of claim 5 wherein the gate conductive layer substantially fills the active trench.

9. The semiconductor device of claim 5 wherein a distance L between a wall of the active trench and a wall of an adjacent body trench is adjusted to minimize fringing gate-to-drain capacitance.

10. A semiconductor device comprising:

a drift region of first conductivity type;

a well region extending above the drift region and having a second conductivity type opposite the first conductivity type;

an active trench extending into the drift region deeper than the well region, the active trench comprising;

dielectric material that lines sidewalls and bottom of the active trench;

a gate conductive layer disposed between the dielectric material;

source regions having the first conductivity type and formed in the well region adjacent the active trench;

a body trench formed adjacent the well region and at least one of the source regions, the body trench being substantially filled with a first conductive material and extending into the drift region deeper than the active trench, a spacing between a sidewall of the body trench and a sidewall of the active trench being about 0.5 μ

m or less; and

a second layer disposed at a depth, the second layer having the second conductivity type, the second layer substantially surrounding the body trench and extending deeper than the well region into the drift region, the second layer having a concentration of the second conductivity type that is greater than a concentration of the second conductivity type of the well region;

wherein disposing the second layer at the depth influences an electric field near the active trench.

11. The semiconductor device of claim 10 wherein the active trench further includes a shield electrode made of a second conductive material formed under the gate conductive layer, the shield electrode inside the active trench being insulated from the gate conductive layer and the sidewalls and bottom of the active trench by a layer of dielectric material.

12. The semiconductor device of claim 10 wherein the body trench is substantially filled with any one of metal, epitaxial material and doped polysilicon that is electrically coupled to the source regions.

13. The semiconductor device of claim 10 wherein the gate conductive layer substantially fills the active trench.

14. The semiconductor device of claim 10 wherein a distance L between the sidewall of the active trench and the sidewall of an adjacent body trench is adjusted to minimize fringing gate-to-drain capacitance.