Integrated MEMS devices with controlled pressure environments by means of enclosed volumes

• US 8,350,346 B1
• Filed: 07/03/2012
• Issued: 01/08/2013
• Est. Priority Date: 07/03/2012
• Status: Active Grant

• Current Assignee: Invensense Incorporated (TDK Corporation)
• Original Assignee: Invensense Incorporated (TDK Corporation)
• Inventors: Huang, Kegang, Lim, Martin, Nasiri, Steven S.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/541,306
• Time in Patent Office: 189 Days
• Field of Search: 257414-420, 257787-790, 438 48- 52, 438455-459
• US Class Current: 257/415
• CPC Class Codes: B81B 2201/025 Inertial sensors not provided for in B81B2201/0235 - B81B2201/0242
• CPC Class Codes: B81B 2201/0271 Resonators; ultrasonic resonators
• CPC Class Codes: B81B 3/0051 For defining the movement, i.e. structures that guide or limit the movement of an element mechanical arrangements for preventing or damping vibration or shock H01H3/60
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body

Abstract

An integrated MEMS device comprises a wafer where the wafer contains two or more cavities of different depths. The MEMS device includes one movable structure within a first cavity of a first depth and a second movable structure within a second cavity of a second depth. The cavities are sealed to maintain different pressures for the different movable structures for optimal operation. MEMS stops can be formed in the same multiple cavity depth processing flow. The MEMS device can be integrated with a CMOS wafer.

Claims

1. An integrated MEMS device comprising

a first structure in a first sealed enclosure;

and

at least one second structure in a second sealed enclosure of greater volume than the first sealed enclosure, wherein the second sealed enclosure is at lower pressure than the first sealed enclosure, wherein a substrate defines part of the first and second sealed enclosures, wherein the substrate contains two or more etched cavities of different depths.

2. The device of claim 1 wherein the substrate is formed from a silicon wafer.

3. The device of claim 1, wherein the substrate comprises an engineered Silicon On Insulator (SOI) wafer.

4. The device of claim 1, wherein the substrate is formed from a cap wafer.

5. The device of claim 1, further comprising at least one feature within one of the first sealed enclosure or the second sealed enclosure to limit motion of one of the first or second structures.

6. The device of claim 5, wherein the at least one feature comprises a MEMS stop.

7. The device of claim 2 further comprising a CMOS wafer mechanically bonded to the silicon wafer.

8. The device of claim 7, wherein the mechanical bond is a eutectic bond.

9. The device of claim 8 wherein the eutectic bond is between aluminum on the CMOS wafer and germanium on the silicon wafer.

10. The device of claim 1, wherein the integrated MEMS device comprises an inertial sensor.

11. The device of claim 1, wherein a bottom surface of one of the etched cavities acts as a MEMS stop.

12. The device of claim 11 wherein the MEMS stop is defined by a shallow cavity depth.

13. A MEMS device comprising:

a substrate, wherein the substrate contains two or more cavities of different depths;

a first structure within a first cavity of a first depth; and

a second structure within a second cavity of a second depth, the first cavity sealed at a first pressure and the second cavity sealed at a second pressure;

a first sealing region around the first cavity; and

a second sealing region around the second cavity to maintain different pressures.

14. The device of claim 13 wherein the substrate is formed from a silicon wafer.

15. The device of claim 13, wherein the substrate comprises an engineered Silicon On Insulator (SOI) wafer.

16. The device of claim 13, wherein the substrate is formed from a cap wafer.

17. The device of claim 13, further comprising at least one feature within one of the first cavity or the second cavity to limit motion of one of the first or second movable structures.

18. The device of claim 17, wherein the at least one feature comprises a MEMS stop.

19. The device of claim 14 further comprising a CMOS wafer mechanically bonded to the silicon wafer.

20. The device of claim 19 wherein there is a eutectic bond between aluminum on the CMOS wafer and germanium on the silicon wafer.

21. The device of claim 13, wherein the substrate comprises a silicon cover wafer.

22. The device of claim 18, wherein the first cavity is deeper than the second cavity and a plurality of MEMS stops are within the first cavity.