Semiconductor device packages with electromagnetic interference shielding

• US 8,350,367 B2
• Filed: 12/16/2008
• Issued: 01/08/2013
• Est. Priority Date: 02/05/2008
• Status: Active Grant

• Current Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Original Assignee: Advanced Semiconductor Engineering Inc (ASE Technology Holding Co., Ltd.)
• Inventors: Chiu, Chi-Tsung, Hung, Chih-Pin, Huang, Jui-Cheng
• Primary Examiner(s): Lee, Eugene
• Assistant Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US12/336,400
• Publication Number:
  US 20090194851A1
• Time in Patent Office: 1,484 Days
• Field of Search: 257/659, 257/660, 257/E23.114, 361/800, 361/816, 361/818
• US Class Current: 257/659
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/49805 the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

Described herein are semiconductor device packages with EMI shielding and related methods. In one embodiment, a semiconductor device package includes: (1) a substrate unit including a grounding element disposed adjacent to a periphery of the substrate unit; (2) a semiconductor device disposed adjacent to an upper surface of the substrate unit; (3) a package body disposed adjacent to the upper surface and covering the semiconductor device; and (4) an EMI shield disposed adjacent to exterior surfaces of the package body and electrically connected to a connection surface of the grounding element. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit, and the connection surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit. The grounding element corresponds to a remnant of a grounding via, and provides an electrical pathway to ground electromagnetic emissions incident upon the EMI shield.

Claims

1. A semiconductor device package, comprising:

a substrate unit including;

an upper surface,

a lower surface,

a lateral surface disposed adjacent to a periphery of the substrate unit, the lateral surface of the substrate unit being substantially planar and fully extending between the upper surface and the lower surface of the substrate unit, and

a grounding element disposed adjacent to the periphery of the substrate unit, the grounding element corresponding to a remnant of a grounding via and including a connection surface that is electrically exposed adjacent to the lateral surface of the substrate unit;

a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device, the package body including exterior surfaces that include a lateral surface, the lateral surface of the package body being substantially co-planar with the lateral surface of the substrate unit; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and electrically connected to the connection surface of the grounding element, the electromagnetic interference shield including a lateral portion that extends around the periphery of the substrate unit, and a lower end of the lateral portion is substantially co-planar with the lower surface of the substrate unit,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

2. The semiconductor device package of claim 1, wherein a height of the grounding element is substantially the same as a thickness of the substrate unit.

3. The semiconductor device package of claim 1, wherein the grounding element partially extends between the upper surface and the lower surface of the substrate unit, such that a height of the grounding element is less than a thickness of the substrate unit.

4. The semiconductor device package of claim 1, wherein a height of the grounding element is in the range of 0.1 mm to 2 mm, and a width of the grounding element is in the range of 75 μ

m to 275 μ

m.

5. The semiconductor device package of claim 1, wherein a height of the grounding element is in the range of 0.1 mm to 1.8 mm, and a width of the grounding element is in the range of 75 μ

m to 275 μ

m.

6. The semiconductor device package of claim 1, wherein the electromagnetic interference shield extends to the lower surface of the substrate unit along all four sides of the substrate unit, such that the lower end of the electromagnetic interference shield fully circumscribes the lower surface of the substrate unit.

7. A semiconductor device package, comprising:

a substrate unit including

a first surface,

a second opposing surface, and

a grounding element at least partially extending between the first surface and the second opposing surface, the grounding element including a first via pad remnant, a second via pad remnant, and a channel remnant extending between the first via pad remnant and the second via pad remnant, at least one of the first via pad remnant, the second via pad remnant, and the channel remnant including a lateral surface exposed at a periphery of the substrate unit;

a semiconductor device disposed adjacent to the first surface of the substrate unit and electrically connected to the substrate unit;

a package body disposed adjacent to the first surface of the substrate unit and covering the semiconductor device and the grounding element, such that the lateral surface of the grounding element is electrically exposed, the package body including exterior surfaces; and

an electromagnetic interference shield disposed adjacent to the exterior surfaces of the package body and contacting the exposed lateral surface of the grounding element, a lower end of the electromagnetic interference shield being substantially co-planar with and fully circumscribing the second opposing surface of the substrate unit,

wherein the grounding element provides an electrical pathway to ground electromagnetic emissions incident upon the electromagnetic interference shield.

8. The semiconductor device package of claim 7, wherein the electromagnetic interference shield extends to the second opposing surface of the substrate unit along all four sides of the substrate unit.

9. The semiconductor device package of claim 7, wherein the first via pad remnant is disposed adjacent to the first surface of the substrate unit, and the second via pad remnant is disposed adjacent to the second opposing surface of the substrate unit.

10. The semiconductor device package of claim 7, wherein the substrate unit further includes a lateral surface extending between the first surface and the second opposing surface, and the lateral surface of the grounding element is electrically exposed adjacent to the lateral surface of the substrate unit.

11. The semiconductor device package of claim 10, wherein the exterior surfaces of the package body include a lateral surface, and the lateral surface of the package body is substantially aligned with the lateral surface of the substrate unit.

12. The semiconductor device package of claim 7, wherein the electromagnetic interference shield is a conformal shield that includes at least one of aluminum, copper, chromium, tin, gold, silver, stainless steel, and nickel.

13. The semiconductor device package of claim 7, wherein the electromagnetic interference shield includes a first layer and a second layer disposed adjacent to the first layer.

14. The semiconductor device package of claim 13, wherein the first layer and the second layer include different electrically conductive materials.

15. The semiconductor device package of claim 7, wherein a thickness of the electromagnetic interference shield is in the range of 1 μ

m to 50 μ

m.

23. The semiconductor device package of claim 7, wherein a lateral profile of the semiconductor device package is substantially planar and is substantially orthogonal with respect to the second opposing surface of the substrate unit.

16. A method of forming a semiconductor device package, comprising:

providing a substrate including an upper surface, a lower surface, and grounding vias at least partially extending between the upper surface and the lower surface;

electrically connecting a semiconductor device to the upper surface of the substrate;

applying a molding material to the upper surface of the substrate to form a molded structure covering the grounding vias and the semiconductor device;

forming cutting slits fully extending through the molded structure and the substrate, the cutting slits being aligned with the substrate, such that;

(a) the substrate is sub-divided to form a separated substrate unit;

(b) the molded structure is sub-divided to form a separated package body disposed adjacent to the substrate unit, the package body including exterior surfaces; and

(c) remnants of the grounding vias correspond to grounding elements disposed adjacent to a periphery of the substrate unit, each of the grounding elements including an exposed connection surface; and

subsequent to forming the cutting slits, applying an electromagnetic interference coating to the exterior surfaces of the package body and the connection surfaces of the grounding elements to form an electromagnetic interference shield.

17. The method of claim 16, wherein a via size of at least one of the grounding vias is in the range of 50 μ

m to 350 μ

m, and a via pad size of at least one of the grounding vias is in the range of 150 μ

m to 550 μ

m.

18. The method of claim 16, wherein a via size of at least one of the grounding vias is in the range of 100 μ

m to 700 μ

m, and a via pad size of at least one of the grounding vias is in the range of 300 μ

m to 1,100 μ

m.

19. The method of claim 16, wherein a spacing of nearest-neighbor ones of the grounding vias is in the range of 0.1 mm to 3 mm.

20. The method of claim 16, further comprising securing the lower surface of the substrate to a tape, and wherein forming the cutting slits is such that the cutting slits extend partially through the tape.

21. The method of claim 16, wherein the substrate unit includes a lateral surface, the exterior surfaces of the package body include a lateral surface, and forming the cutting slits is such that the lateral surface of the package body is substantially aligned with the lateral surface of the substrate unit.

22. The method of claim 16, wherein a width of at least one of the cutting slits is in the range of 100 μ

m to 600 μ

m.

24. The method of claim 16, wherein the electromagnetic interference shield includes a lateral portion fully extending between an upper surface and a lower surface of the substrate unit, the lateral portion having a lower end that is substantially co-planar with the lower surface of the substrate unit.