Semiconductor device including electronic component coupled to a backside of a chip

• US 8,350,382 B2
• Filed: 09/21/2007
• Issued: 01/08/2013
• Est. Priority Date: 09/21/2007
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Fürgut, Edward, Mahler, Joachim, Bauer, Michael
• Primary Examiner(s): Arroyo, Teresa M
• Application Number:
  US11/859,353
• Publication Number:
  US 20090079065A1
• Time in Patent Office: 1,936 Days
• Field of Search: 257/777, 257/724, 257/774, 257/686, 257/751, 257/750, 257/723, 257/924, 257/778, 257/E23.023, 257/E21.531, 257/E23.085, 257/E25.027, 257/E25.006, 257/E25.021, 257/E25.013
• US Class Current: 257/724
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/051 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

Claims

1. An electronic device comprising:

a substrate;

at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate; and

means for electrically coupling at least one electronic component to the backside of the chip such that the electronic component is in electrical communication with the substrate,

wherein the means for electrically coupling at least one electronic component to the backside of the chip comprises a metallization layer deposited on the chip between the backside of the chip and the electronic component, the metallization layer comprising a multi-layer structure including a diffusion barrier layer, and

wherein each layer in the multi-layer structure is a metal layer, the multi-layer structure includes at least four metal layers, at least three of the metal layers have a same surface area parallel to the backside of the at least one chip, and the diffusion barrier layer comprises a topmost metal layer of the multi-layer structure opposite a bottommost metal layer contacting the chip.

2. A semiconductor package comprising:

a substrate;

at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate;

a conductive layer coupled to the backside of the at least one chip, the conductive layer comprising a multilayer stack including at least four metal layers; and

at least one electronic component coupled to the conductive layer and in electrical communication with the substrate,

wherein at least three of the metal layers have a same surface area parallel to the backside of the at least one chip, and wherein a topmost metal layer of the multilayer stack opposite a bottommost metal layer contacting the chip comprises a diffusion barrier layer.

3. The semiconductor package of claim 2, wherein the diffusion barrier layer comprises titanium.

4. The semiconductor package of claim 2, wherein the first side of at least one chip is an active side, the at least one chip comprising vias extending between the active side and the backside, the active side flip chip bonded to the substrate by bumps, and the at least one electronic component electrically communicating with the substrate through the vias and the bumps.

5. The semiconductor package of claim 2, wherein the substrate comprises a redistribution layer and the at least one chip comprises an embedded chip electrically coupled to the redistribution layer, the at least one chip comprising vias extending between the first side and the backside, and the at least one electronic component electrically communicating with the redistribution layer through the vias.

6. The semiconductor package of claim 2 wherein the at least one electronic component comprises a passive electrical component selected from the group consisting of a resistor, an inductor, and a capacitor.

7. The semiconductor package of claim 2, wherein the at least one electronic component comprises an active electrical component.

8. The semiconductor package of claim 2, wherein the conductive layer is deposited over less than an entirety of the backside of the at least one chip.

9. The semiconductor package of claim 2, wherein the semiconductor package has a thickness less than approximately 200 microns.