Reduced bottom roughness of stress buffering element of a semiconductor component

• US 8,350,385 B2
• Filed: 07/15/2008
• Issued: 01/08/2013
• Est. Priority Date: 07/30/2007
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Hochstenbach, Hendrik
• Primary Examiner(s): Pham, Long
• Application Number:
  US12/670,562
• Publication Number:
  US 20100187688A1
• Time in Patent Office: 1,638 Days
• Field of Search: 257/738, 257/737, 257/E21.59, 257/E23.023, 257/E23.175, 438/613
• US Class Current: 257/738
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05007 comprising a core and a coating
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/3142 Sealing arrangements between parts, e.g. adhesion promotors
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 Fully indexed content
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01012 Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

The present invention relates to a stress buffering package (49) for a semiconductor component, with a semiconductor substrate (52); an I/O pad (54), electrically connected to the semiconductor substrate (52); a stress buffering element (74) for absorbing stresses, electrically connected to the I/O pad (54); an underbump metallization (70), electrically connected to the stress buffering element (74); a solder ball (60), electrically connected to the underbump metallization (70); a metal element (61) between the solder ball (60) and the semiconductor substrate (52); a passivation layer (56, 58), which protects the semiconductor substrate (52) and the metal element (61) and which at least partially exposes the I/O pad (54); characterized in that a roughness of an interface between the stress buffering element (74) and the passivation layer (56, 58) is lower than a roughness of an interface between the metal element (61) and the passivation layer (56, 58). Furthermore the invention relates a method for manufacturing a stress buffering package (49) for a semiconductor component.

Claims

1. A stress buffered semiconductor component, comprising:

an electric circuit comprising a plurality of devices defined in a semiconductor substrate and an interconnection structure defined in one or more metal layers on the semiconductor substrate and protected by a passivation layer on top of the upper of the one or more metal layers, which passivation layer partially exposes an I/O pad being electrically connected to the electric circuit;

a stress buffering element adapted for absorbing stresses on the I/O pad;

an underbump metallization, electrically connected to the stress buffering element;

characterized in that a roughness of an interface between the stress buffering element and the passivation layer is lower than a roughness of an interface between the upper metal layer and the passivation layer.

2. A component as claimed in claim 1, characterized in that an upper side of the passivation layer facing away from the upper metal layer is more flat than a lower side of the passivation layer facing towards the upper metal layer.

5. A component as claimed in claim 1, wherein the number of I/O pads exceeds an array of 7×

7.

6. A component as claimed in claim 1, wherein the electric circuit comprises a digital signal processor (DSP).

7. A component as claimed in claim 1, wherein the interconnection structure further comprises dielectric layers of a low-K material.

8. A component as claimed in claim 1, wherein at least one of the devices is a transistor with a channel length of at most 65 nm.

9. A component as claimed in claim 1 which is provided with a solder ball on the underbump metallisation.

10. A semiconductor component as claimed in claim 1, wherein the electric circuit is an audio circuit and preferably comprising a circuit for receiving and amplifying an audio signal.

11. An assembly comprising a board and the component as claimed in claim 10, which is electrically connected to the board via the solder balls.

13. A component of claim 1, wherein the interconnect structure includes a dielectric layer of a low-K material.

3. A stress buffered semiconductor component, comprising:

an electric circuit comprising a plurality of devices defined in a semiconductor substrate and an interconnection structure defined in one or more metal layers on the semiconductor substrate and protected by a passivation layer on top of the upper of the one or more metal layers, which passivation layer partially exposes an I/O pad being electrically connected to the electric circuit;

a stress buffering element adapted for absorbing stresses on the I/O pad;

an underbump metallization, electrically connected to the stress buffering element;

characterized in that a roughness of an interface between the stress buffering element and the passivation layer is lower than a roughness of an interface between the upper metal layer and the passivation layer, and in that the passivation layer comprises a first layer in contact with the upper metal layer and a second layer that extends from the upper side of the first layer.

4. A component as claimed in claim 3, characterized in that the first layer serves as a roughness-lowering or planarization layer for lowering the roughness of the interface between the stress buffering element and the passivation layer.

12. A stress buffered semiconductor component, comprising:

an electric circuit comprising a plurality of devices defined in a semiconductor substrate and an interconnection structure defined in one or more metal layers on the semiconductor substrate and protected by a passivation layer on top of the upper of the one or more metal layers, which passivation layer partially exposes an I/O pad being electrically connected to the electric circuit;

a stress buffering element adapted for absorbing stresses on the I/O pad;

an underbump metallization, electrically connected to the stress buffering element;

characterized in that a roughness of an interface between the stress buffering element and the passivation layer is lower than a roughness of an interface between the upper metal layer and the passivation layer and, wherein the passivation layer includes a planarization layer for lowering the roughness of the interface between the stress buffering element and the passivation layer.

14. A stress buffered semiconductor component, comprising:

an electric circuit comprising a plurality of devices defined in a semiconductor substrate and an interconnection structure defined in one or more metal layers on the semiconductor substrate and protected by a passivation layer on top of the upper of the one or more metal layers, which passivation layer partially exposes an I/O pad being electrically connected to the electric circuit, the passivation layer including a first portion defined on top of an element in the upper one of the one or more metal layers and includes a second portion adjacent to the element;

a stress buffering element adapted for absorbing stresses on the I/O pad;

an underbump metallization, electrically connected to the stress buffering element; and

characterized in that an upper surface of the first and second portions forming an angle that is less than 50 degrees, and a roughness of an interface between the stress buffering element and the passivation layer is lower than a roughness of an interface between the upper metal layer and the passivation layer.