Single supply digital voltage level shifter

• US 8,350,592 B1
• Filed: 01/23/2012
• Issued: 01/08/2013
• Est. Priority Date: 01/23/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Malhan, Bipin B., Goyal, Gaurav, Lohani, Umesh Chandra
• Primary Examiner(s): TRAN, ANH Q
• Application Number:
  US13/356,626
• Time in Patent Office: 351 Days
• Field of Search: 326/62, 326/68, 326/80, 326/81, 327/333
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

A single-supply digital voltage level shifter has a first inverter having a first input for receiving an input signal with a first voltage swing, and a first output for outputting a first output signal. A second inverter has a second input for receiving the first output signal, and a second output for outputting a second output signal with a second voltage swing, where the second output signal is a level-shifted version of the input signal. A comparison stage includes a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal. A control stage is connected in a circuit branch of the first inverter and has a control stage switch that assumes a non-conducting state dependent on a logical state of the comparison stage output control signal.

Claims

1. A single supply digital voltage level shifter comprising:

a first inverter having a first input for receiving an input signal of a first voltage swing, and a first output for outputting a first output signal;

a second inverter having a second input for receiving the first output signal, and a second output for outputting a second output signal of a second voltage swing, the second output signal being a level-shifted version of the input signal;

a comparison stage having a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal; and

a control stage connected in a circuit branch of the first inverter, the control stage having a control stage switch that assumes a non-conducting state dependent on a logical state of the comparison stage output control signal.

2. The voltage level shifter of claim 1, wherein the comparison stage output control signal assumes a logical high state when the input signal transitions to a logical high state.

3. The voltage level shifter of claim 1, wherein the comparison stage comprises a first switch connected between the second comparison stage input and the comparison stage output, wherein the first switch is controlled by the input signal.

4. The voltage level shifter of claim 3, wherein the first switch is a switch in a first switch pair, the first switch pair further comprising a second switch connected in parallel with the first switch of the first switch pair, wherein the second switch is controlled by the first output signal.

5. The voltage level shifter of claim 4, the comparison stage further comprising:

a third comparison stage input for receiving the first output signal; and

a second switch pair connected in parallel between the third comparison stage input and the comparison stage output, a first switch of the second switch pair controlled by the input signal, and a second switch of the second switch pair is controlled by the first output signal.

6. The voltage level shifter of claim 5, wherein the first switch of the second switch pair comprises a P-type MOSFET and the second switch of the second switch pair comprises an N-type MOSFET.

7. The voltage level shifter of claim 4, wherein the first switch of the first switch pair comprises an N-type MOSFET and the second switch of the first switch pair comprises a P-type MOSFET.

8. The voltage level shifter of claim 1, wherein the comparison stage output control signal assumes a logical low state when the input signal transitions to a logical low state and, thereafter, the comparison stage output control signal assumes a logical high state while the input signal maintains a logical low state.

9. The voltage level shifter of claim 1, further comprising:

a third inverter having a third input for receiving the first output signal, and a third output for outputting an output driver signal of the second voltage swing, the output driver signal being a level-shifted version of the input signal.

10. The voltage level shifter of claim 1, wherein the control stage switch comprises a switch control input connected to the comparison stage output.

11. The voltage level shifter of claim 10, wherein the control stage switch assumes a non-conducting state when the comparison stage output signal is in a logical high state.

12. The voltage level shifter of claim 11, wherein the control stage further comprises a second control stage switch connected in parallel with the control stage switch, wherein the second control stage switch assumes a non-conducting state dependent on a logical state of the second output signal.

13. The voltage level shifter of claim 12, wherein the second control stage switch comprises a switch control input connected to the second output.

14. A method of operating a single supply digital voltage level shifter, the method comprising:

providing a first inverter having a first input for receiving an input signal of a first voltage swing, and a first output for outputting a first output signal;

providing a second inverter having a second input for receiving first output signal, and a second output for outputting a second output signal of a second voltage swing, the second output signal being a level-shifted version of the input signal;

providing a comparison stage having a first comparison stage input for receiving the input signal, a second comparison stage input for receiving the second output signal, and a comparison stage output for outputting a comparison stage output control signal;

providing a control stage connected to a circuit branch of the first inverter, the control stage having a control stage switch;

applying the input signal to the first input; and

controlling the control stage switch to assume a non-conducting state dependent on a logical state of the comparison stage output control signal.

15. The method of claim 14, further comprising controlling the comparison stage such that the comparison stage output control signal assumes a logical high state when the input signal transitions to a logical high state.

16. The method of claim 14, further comprising providing a first switch connected between the second comparison stage input and the comparison stage output, the method further comprising controlling the first switch using the input signal.

17. The method of claim 16, wherein the first switch is a switch in a first switch pair, the first switch pair further comprising a second switch connected in parallel with the first switch of the first switch pair, the method further comprising controlling the second switch using the first output signal.

18. The method of claim 17, further comprising:

providing the comparison stage with a third comparison stage input for receiving the first output signal;

providing the comparison stage with a second switch pair connected in parallel between the third comparison stage input and the comparison stage output;

controlling a first switch of the second switch pair using the input signal; and

controlling a second switch of the second switch pair using the first output signal.

19. The method of claim 14, further comprising controlling the comparison stage such that the comparison stage output control signal assumes a logical low state when the input signal transitions to a logical low state and, controlling the comparison stage such that the comparison stage output control signal assumes a logical high state while the input signal maintains a logical low state.

20. The method of claim 14, further comprising:

providing a third inverter having a third input for receiving the first output signal, and a third output that outputs an output driver signal of the second voltage swing, the output driver signal being a level-shifted version of the input signal.