Amplifiers and related biasing methods and devices

• US 8,350,624 B2
• Filed: 09/01/2010
• Issued: 01/08/2013
• Est. Priority Date: 09/01/2010
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Lam, Fleming
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US12/807,365
• Publication Number:
  US 20120049956A1
• Time in Patent Office: 860 Days
• Field of Search: 330/253, 330/255, 330/261, 330/258, 330/296, 330/277
• US Class Current: 330/261
• CPC Class Codes: H03F 1/0272 by using a signal derived from the output signal
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/471 the voltage being sensed
• CPC Class Codes: H03F 2203/30063 A differential amplifier being used in the bias circuit or in the control circuit of the SEPP-amplifier
• CPC Class Codes: H03F 2203/45024 the differential amplifier amplifying transistors are cascode coupled transistors
• CPC Class Codes: H03F 2203/45244 the differential amplifier contains one or more explicit bias circuits, e.g. to bias the tail current sources, to bias the load transistors
• CPC Class Codes: H03F 2203/45311 the common gate stage of a cascode dif amp being implemented by multiple transistors
• CPC Class Codes: H03F 2203/45418 the CMCL comprising a resistor addition circuit
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: H03F 3/45179 using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/45188 Non-folded cascode stages
• CPC Class Codes: H03F 3/45708 Controlling the common source circuit of the differential amplifier

Abstract

Biasing methods and devices for amplifiers are described. The described methods generate bias voltages proportional to the amplifier output voltage to control stress voltages across transistors used within the amplifier.

Claims

1. A biasing method comprising the steps of:

providing an amplifier having an amplifier output node;

sensing an output voltage at the amplifier output node;

generating one or more bias voltages proportional to the output voltage to bias the amplifier;

providing a transistor-resistor stack comprising a plurality of MOSFET devices arranged in a cascode configuration and serially connected with an in-series arrangement of a plurality of resistors wherein;

a gate of one of the MOSFET devices is connected with the amplifier output node to sense the output voltage; and

a current proportional to the output voltage is generated through the plurality of resistors to generate the one or more bias voltages.

2. A bias circuit connectable, during operation, to an output stage of an amplifier comprising a plurality of amplifier MOSFET devices to produce an output voltage at an amplifier output node, the bias circuit comprising:

a sensing section to sense the amplifier output voltage comprising a plurality of sensing MOSFET devices arranged in a cascode configuration wherein a gate terminal of one of the plurality of the sensing MOSFET devices is connected with the amplifier output node; and

a biasing section connected with the sensing section to provide, during operation, bias voltages proportional to the output voltage to gate terminals of the amplifier MOSFET devices.

3. A bias circuit connectable, during operation, to an amplifier comprising a plurality of amplifier MOSFET devices to produce an output voltage at an amplifier output node, the bias circuit comprising a plurality of biasing MOSFET devices arranged in a cascode configuration and serially connected with an in-series arrangement of a plurality of resistors wherein during operation:

a gate terminal of one of the biasing MOSFET devices is connected with the amplifier output node; and

a current proportional the amplifier output voltage is generated through the plurality of resistors to provide bias voltages to gate terminals of the plurality of amplifier MOSFET devices.

4. A biasing method comprising the steps of:

providing a differential amplifier with an input common mode node;

sensing an input common mode voltage at the input common mode node;

producing one or more bias voltages proportional to the input common mode voltage to bias the differential amplifier, and

providing a transistor-resistor stack comprising a plurality of MOSFET devices arranged in a cascode configuration and serially connected with an in-series arrangement of a plurality of resistors wherein;

a gate of one of the plurality of MOSFET devices is connected with the differential amplifier input common mode node to sense the input common mode voltage; and

a current proportional to the output voltage is generated through the plurality of resistors to produce the one or more bias voltages.

5. A bias circuit connectable, during operation, to a differential amplifier comprising a plurality of amplifier MOSFET devices to produce an output voltage at an amplifier input common mode node, the bias circuit comprising a plurality of biasing MOSFET devices arranged in a cascode configuration and serially connected with an in-series arrangement of a plurality of resistors wherein during operation:

a gate terminal of one of the biasing MOSFET devices is connected with the amplifier input common mode node; and

a current proportional the amplifier input common mode voltage is generated through the plurality of resistors to provide bias voltages to gate terminals of the plurality of amplifier MOSFET devices.

6. An amplifier comprising:

an amplifier differential output stage having two complementary sides, each side having an output node and comprising a stack of N-type and P-type MOSFET transistors arranged in series; and

two biasing circuits each comprising;

a first stack comprising;

a plurality of MOSFET devices of a first type arranged in a cascode configuration; and

a plurality of series resistor arranged in series with the plurality of MOSFET devices of the first type; and

a second stack comprising;

a plurality of MOSFET devices of a second type, opposite of the first type, arranged in a cascode configuration; and

a plurality of series resistor arranged in-series with the plurality of MOSFET devices of the second type;

wherein in each biasing circuit;

a gate terminal of one of the plurality of MOSFET devices of the first type and a gate terminal of one of the plurality of MOSFET devices of the second type are connected with the output node of one of the two complementary sides and wherein during operation;

currents proportional to output voltages generated at the output nodes flow through the series resistors within the biasing circuits to produce bias voltages for gate terminals of the N-type and P-type MOSFET transistors of the amplifier differential output stage.

7. An amplifier comprising:

a) an amplifier differential input stage having an input common mode voltage node and a plurality of amplifier MOSFET devices; and

b) a biasing circuit comprising;

b1) a first stack comprising;

a plurality of biasing MOSFET devices of a first type arranged in a cascode configuration; and

a plurality of series resistors arranged in series with the plurality of biasing MOSFET devices of the first type; and

b2) a second stack comprising;

a plurality of biasing MOSFET devices of a second type, opposite of the first type, arranged in a cascode configuration; and

a plurality of series resistors arranged in-series with the plurality of biasing MOSFET devices of the second type;

wherein;

a gate terminal of one of the plurality of biasing MOSFET devices of the first type and gate terminal of one of the plurality of biasing MOSFET devices of the second type are connected with the input common mode node of the amplifier input differential stage and wherein during operation;

currents proportional to an input common mode voltage generated at the input common mode node flow through the series resistors within the biasing circuit to produce bias voltages to gate terminals of the plurality of the amplifier MOSFET devices.