Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
First Claim
1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
- a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction;
a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes;
each adjacent pair of the second conductive lines being disposed around a corresponding row of first conductive lines in the x-direction for operating exclusively therewith;
a plurality of non-volatile re-programmable memory elements individually connected between the first conductive lines and second conductive lines adjacent the crossings thereof at the plurality of locations; and
a plurality of select devices arranged to individually couple a selected row of first conductive lines to a plurality of third conductive lines.
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Accused Products
Abstract
A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. A two-dimensional array of bit lines to which the memory elements of all planes are connected is oriented vertically from the substrate and through the plurality of planes. A single-sided word line architecture provides a word line exclusively for each row of memory elements instead of sharing one word line between two rows of memory elements thereby avoids linking the memory element across the array across the word lines. While the row of memory elements is also being accessed by a corresponding row of local bit lines, there is no extension of coupling between adjacent rows of local bit lines and therefore leakage currents beyond the word line.
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Citations
18 Claims
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1. A data memory including memory elements arranged in a three-dimensional pattern defined by rectangular coordinates having x, y and z-directions and with a plurality of parallel planes stacked in the z-direction, the memory further comprising:
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a plurality of first conductive lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x-direction and columns in the y-direction; a plurality of second conductive lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the first plurality of conductive lines in the individual planes, wherein the first and second conductive lines cross adjacent each other at a plurality of locations across the individual planes; each adjacent pair of the second conductive lines being disposed around a corresponding row of first conductive lines in the x-direction for operating exclusively therewith; a plurality of non-volatile re-programmable memory elements individually connected between the first conductive lines and second conductive lines adjacent the crossings thereof at the plurality of locations; and a plurality of select devices arranged to individually couple a selected row of first conductive lines to a plurality of third conductive lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method of operating a re-programmable non-volatile memory system, comprising:
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utilizing at least one integrated circuit that includes a three-dimensional pattern of memory elements defined by rectangular coordinates having x, y and z-directions and which comprises; a plurality of parallel planes stacked in the z-direction on top of a semiconductor substrate; a plurality of conductive local bit lines elongated in the z-direction through the plurality of planes and arranged in a two-dimensional rectangular array of rows in the x and columns in the y-directions; a plurality of word lines elongated in the x-direction across individual planes and spaced apart in the y-direction between and separated from the plurality of local bit lines in the individual planes, wherein the local bit lines and word lines cross adjacent each other at a plurality of locations across the individual planes; each adjacent pair of word lines of the plurality of word lines being disposed around a corresponding row of local bit lines in the x-direction for operating exclusively therewith; a plurality of re-programmable non-volatile memory elements individually connected between the local bit lines and the word lines adjacent the crossings thereof at the plurality of locations; and a plurality of select devices arranged to individually couple a selected row of local bit lines to a plurality of global bit lines in response to select control signals; applying select control signals to the plurality of select devices in order to connect selected row of local bit lines to individual ones of the global bit lines, and causing a selected one or more of the plurality of memory elements to simultaneously change between their at least first and second states by applying one of the first and second stimuli through the word lines and global bit lines between which the selected one or more of the plurality of memory elements are operably connected. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification