Dynamic sense current supply circuit and associated method for reading and characterizing a resistive memory array
First Claim
1. An electronic circuit for characterizing a resistive memory array, said circuit comprising:
- a first current mirror sub-circuit, said first current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control;
a second current mirror sub-circuit, said second current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control;
a reference current terminal to apply an external reference current to said first current mirror sub-circuit to generate a first current through said first current mirror sub-circuit;
an interconnection to couple said first current to said second current mirror sub-circuit;
a sense current terminal to apply a sense current passed through said second current mirror sub-circuit to a memory cell under test; and
a digital circuit element to generate a digital signal indicative of electrical current flowing through said memory cell under test.
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Abstract
A dynamic sense current supply circuit and an associated method for rapidly characterizing a resistive memory array is disclosed. In one embodiment, the disclosed circuit comprises a first and second dynamically programmable current mirror sub-circuit. Responsive to a bank of control signals, each dynamically programmable current mirror sub-circuit provides a dynamically adjustable current scaling factor. These scaling factors are used to scale a supplied reference current to generate a plurality of sense currents which can be used within a plurality of read operations on a resistive memory array. A digital circuit is also provided to sense and store the result of each read operation.
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Citations
14 Claims
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1. An electronic circuit for characterizing a resistive memory array, said circuit comprising:
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a first current mirror sub-circuit, said first current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control; a second current mirror sub-circuit, said second current mirror sub-circuit comprising a first stage and a second stage, said second stage comprising at least two current branches and wherein at least one of said current branches is responsive to an enable control; a reference current terminal to apply an external reference current to said first current mirror sub-circuit to generate a first current through said first current mirror sub-circuit; an interconnection to couple said first current to said second current mirror sub-circuit; a sense current terminal to apply a sense current passed through said second current mirror sub-circuit to a memory cell under test; and a digital circuit element to generate a digital signal indicative of electrical current flowing through said memory cell under test. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification