Method for non-volatile memory with background data latch caching during read operations

• US 8,351,269 B2
• Filed: 10/06/2011
• Issued: 01/08/2013
• Est. Priority Date: 04/01/2005
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Li, Yan
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US13/267,689
• Publication Number:
  US 20120026791A1
• Time in Patent Office: 460 Days
• Field of Search: 365/185.21, 365/185.12
• US Class Current: 365/185.21
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/3042 being part of a memory device, e.g. cache DRAM
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 2207/2245 Memory devices with an internal cache buffer
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.

Claims

1. A non-volatile memory device having addressable pages of memory cells on associated wordlines, comprising:

a set of data latches provided for each memory cell of an addressed page, said set of data latches having capacity for latching a predetermined number of bits;

a state machine for controlling memory operations including;

a read operation on a designated group of pages;

sensing and latching a page of data in each of a series of reading cycles, wherein said sensing and latching in a current reading cycle is directed to a current page of data on a current wordline and is responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom;

said sensing and latching arranged to, in the current reading cycle, other than the first reading cycles, sense and latch the current page while outputting a previous page sensed and latched in a just passed reading cycle;

preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and

wherein said preemptively sensing and latching is arranged to, while the previous page is output, preemptively sense and latch the prerequisite data for the current page prior to the current reading cycle and to preemptively sense and latch the prerequisite data for a next page that is to be read while the previous page is output.

2. The non-volatile memory of claim 1, wherein the memory cells each stores one bit of data.

3. The non-volatile memory of claim 1, wherein the memory cells each stores more than one bit of data and each page of memory cells on a wordline is associated with more than one page of binary data corresponding to the individual bits of each memory cell.

4. A method of reading a non-volatile memory having addressable pages of memory cells on associated wordlines, comprising:

sensing and latching a page of data in each of a series of reading cycles, wherein said sensing and latching in a current reading cycle are directed to a current page of data on a current wordline and are performed responsive to prerequisite data from an adjacent wordline so as to correct for any perturbation effects therefrom;

preemptively sensing and latching the prerequisite data for the current page prior to the current reading cycle; and

performing in the current reading cycle, other than a first reading cycle, while outputting a previous page sensed and latched in a just passed reading cycle, said sensing and latching of the current page and preemptive sensing and latching of the prerequisite data for a next page that is to be sensed while outputting a previous page sensed and latched in the just passed reading cycle.

5. The method of claim 4, wherein the memory cells each stores one bit of data.

6. The method of claim 4, wherein the memory cells each stores more than one bit of data and each page of memory cells on a wordline is associated with more than one page of binary data corresponding to the individual bits of each memory cell.

7. The method of claim 6, wherein said sensing and latching of the prerequisite data for the current page further comprises:

outputting a first flag obtained as part of the prerequisite data from said prerequisite sensing;

adjusting the prerequisite data responsive to the first flag; and

latching the adjusted prerequisite data to indicate whether corrections need to be made for the current page.

8. The method of claim 7, wherein the first flag indicates whether the prerequisite page of memory cells on the adjacent wordline has been programmed with all the bits.

9. The method of claim 8, wherein:

when the first flag indicates that the adjacent wordline has not been programmed with all the bits, adjusting the prerequisite data to indicate no correction is needed.

10. The method of claim 8, wherein:

when the first flag indicates that the adjacent wordline has been programmed with all the bits, adjusting the prerequisite data to indicate that correction is needed.

11. The method of claim 6, wherein said sensing and latching of a current page further comprises:

performing said sensing of the current page with corrections from the adjusted prerequisite data to obtain a sensed current page;

outputting a second flag obtained as part of the sensed current page;

responsive to the second flag, refreshing the sensed current page either by leaving the sensed current page unchanged, or adjusting the sensed current page to a predetermined value, or replacing with a new sensed current page obtained by repeating said sensing of the current page under another set of sensing conditions; and

latching the refreshed sensed current page for outputting in the next reading cycle.

12. The method of claim 11, wherein said sensing of the current page for those memory cells that needs correction as indicated by the adjusted prerequisite data is performed at a wordline voltage with a predetermined boost.

13. The method of claim 11, wherein the second flag indicates whether the current page of memory cells on the current wordline has been programmed with all the bits.

14. The method of claim 13, wherein:

when the second flag indicates that the current page has been programmed with all the bits, said refreshing the sensed current page is a null operation by leaving the sensed current page unchanged.

15. The method of claim 13, wherein:

the memory cells each stores two bits of data;

the page of memory cells is constituted from a lower-bit page and an upper-bit page; and

when the second flag indicates that the current page has not been programmed with all the bits, and the current page being sensed is an upper-bit page, said refreshing the sensed current page is by resetting all bits of the sensed current page to a predetermined bit value indicating the upper-bit page has not been programmed.

16. The method of claim 13, wherein:

the memory cells each stores two bits of data;

the page of memory cells is constituted from a lower-bit page and an upper-bit page; and

when the second flag indicates that the current page has not been programmed with all the bits, and the current page being sensed is a lower-bit page, said refreshing the sensed current page is by sensing the current page relative to another predetermined reference.