Erased page detection

• US 8,351,290 B1
• Filed: 09/10/2009
• Issued: 01/08/2013
• Est. Priority Date: 09/12/2008
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Marvell International Limited (Marvell Technology Group Limited)
• Inventors: Huang, ChengKuo, Au, Siu-Hung Fred
• Primary Examiner(s): NGUYEN, STEVE N
• Application Number:
  US12/557,311
• Time in Patent Office: 1,216 Days
• Field of Search: None
• US Class Current: 365/218
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

A memory device and method, such as a flash memory device and method, includes a memory having a plurality of nonvolatile memory cells for storing stored values of user data. The memory device and method includes a memory controller for controlling the memory. The memory controller includes an encoder for encoding user write data for storage of code values as the stored values in the memory. The encoder includes an inserter for insertion of an indicator as part of the stored values for use in determining when the stored values are or are not in an erased state. The memory controller includes a decoder for reading the stored values from the memory to form user read data values when the stored values are not in the erased state.

Claims

1. A memory device comprising:

a memory including a plurality of nonvolatile memory cells; and

a memory controller comprising

an encoder configured to (i) receive user write data and (ii) encode the user write data to generate encoded data,

wherein the encoder includes an inserter to insert an indicator in the user write data prior to encoding the user write data,

wherein the inserted indicator indicates whether or not the encoded data is in an erased state,

wherein data stored in the memory is in the erased state if the data is intended to erase a section of the memory in which the data is stored, and

wherein the encoded data is stored in the memory, and

a decoder configured to (i) read the encoded data from the memory, (ii) generate user read data from the encoded data read from the memory,

wherein the decoder includes a count detector configured to (i) count a number of 1'"'"'s in the encoded data read from the memory, (ii) determine that the encoded data is in the erased state if the counted number of 1'"'"'s is less than a threshold,

wherein the user write data has N number of data bits, wherein N is an integer, and

wherein the threshold is equal to N/2.

2. The memory device of claim 1, wherein the decoder includes a detector for detecting the indicator in the encoded data read from the memory.

3. A memory device comprising:

a memory including a plurality of nonvolatile memory cells; and

a memory controller comprising

an encoder configured to (i) receive user write data and (ii) encode the user write data to generate encoded data,

wherein the encoder includes an inserter,

wherein the inserter includes a flag appender to append a flag in the user write data prior to encoding the user write data,

wherein the inserted flag indicates whether or not the encoded data is in an erased state, wherein the encoded data is stored in the memory,

wherein data stored in the memory is in the erased state if the stored data is intended to erase a section of the memory in which the data is stored, and

a decoder configured to (i) read the encoded data from the memory, (ii) generate user read data from the encoded data read from the memory,

wherein the decoder includes a detector for detecting the flag in the user read data,

wherein the flag is a 2-bit flag, and

wherein “

10” and

“

01”

states of the 2-bit flag indicate that the encoded data is not in the erased state.

4. The memory device of claim 3, wherein:

the encoder includes a cyclic redundancy code generator for generating a cyclic redundancy code (CRC) value, wherein the inserter includes a converter for converting the CRC value to a converted CRC′

value to indicate the presence of a code word in the user write data, and

the decoder includes

a CRC′

detector for detecting the converted CRC′

value to sense the presence of the code word, and

a CRC′

to CRC converter for converting the converted CRC′

value to the CRC value.

5. The memory device of claim 3, wherein:

the user write data has a plurality of first blocks,

the encoder comprises;

an inverter for inverting each of the plurality of first blocks to provide corresponding plurality of inverted second blocks,

a 1'"'"'s counter for counting the 1'"'"'s for each first block to determine if each first block has more 1'"'"'s than 0'"'"'s,

a selector for selecting first blocks or second blocks, wherein (i) a first block is selected if the first block does not have more 1'"'"'s than 0'"'"'s and (ii) a second block is selected if the corresponding first block has more 1'"'"'s than 0'"'"'s, and

a flag store for storing flags to indicate when second blocks are selected, wherein the memory controller causes the flags, the selected first blocks and the selected second blocks to be written into and read from the memory as stored flags and stored blocks, and

the decoder comprises;

a register for receiving each of the stored blocks as received blocks,

an inverter for inverting the received blocks to form inverted stored blocks, and

a selector for selecting received blocks or inverted stored blocks where one of the received blocks is selected when a corresponding one of the flags is not set and the corresponding one of the inverted stored blocks is selected when the corresponding one of the stored flags is set.

6. The memory device of claim 3, wherein:

the user write data has a plurality of first blocks BLK_1, BLK_2, . . . , BLK_B, where BLK_b represents each of the first blocks for b=1, 2, . . . , B,

the encoder comprises;

an inverter for inverting the first blocks BLK_1, BLK_2, . . . , BLK_B to provide corresponding second blocks BLK_1(I), BLK_2(I), . . . , BLK_B(I) where BLK_b(I) represents each of the inverted second blocks for b=1, 2, . . . , B,

a 1'"'"'s counter for counting the 1'"'"'s for each first block BLK_b for b=1, 2, . . . , B to determine if each BLK_b has more 1'"'"'s than 0'"'"'s,

a selector for selecting first blocks or second blocks for b=1, 2, . . . , B where the first block BLK_b is selected when the first block BLK_b does not have more 1'"'"'s than 0'"'"'s and the corresponding second block BLK_b(I) is selected when the first block BLK_b has more 1'"'"'s than 0'"'"'s, and

a flag store for storing for b=1, 2, . . . , B flags to indicate when corresponding second blocks BLK_b(I) are selected, wherein the memory controller causes the flags, the selected first blocks and the selected second blocks to be written into and read from the memory as stored flags and stored blocks BLK-s_1, BLK-s_2, . . . , BLK-s_B where BLK-s_b represents each of the stored blocks for b=1, 2, . . . , B; and

the decoder comprises;

a register for receiving each of the stored blocks BLK-s_b for b=1, 2, . . . , B, an inverter for inverting the stored blocks BLK-s_1, BLK-s_2, . . . , BLK-s_B to form

inverted stored blocks BLK-s_1(I), BLK-s_2(I), . . . , BLK-s_B(I) where BLK-s_b(I) represents each of the inverted stored blocks for b=1, 2, . . . , B, and

a selector for selecting stored blocks BLK-s_1, BLK-s_2, . . . , BLK-s_B or inverted stored blocks BLK-s_1(I), BLK-s_2(I), . . . , BLK-s_B(I) for b=1, 2, . . . , B where the stored block BLK-s_—

b is selected when the flag is not set and the inverted stored block BLK-s_b(I) is selected when the stored flag is set.

7. The memory device of claim 3, wherein;

the encoder comprises;

a conditional inverter for (i) selectively inverting user write data to form inverted user write data, wherein the selective inversion is based on a number of 1'"'"'s in the user write data, and (ii) appending an identifying bit for indicating the inversion, wherein the user write data or the inverted user write data are stored in the memory after being encoded,

the decoder comprises an erased page detector for detecting an erased page as a function of the number of 1'"'"'s in the encoded data.

8. The memory device of claim 7 wherein

the conditional inverter comprises:

a counter for counting the number of 1'"'"'s in an input sector having a sector length of N, where N is a positive integer, to form a 1'"'"'s count,

a comparator for comparing the 1'"'"'s count with N/2 to determine if the 1'"'"'s count is greater than N/2,

an inverter for inverting the sector if the 1'"'"'s count is greater than N/2,

an appender for appending a control bit as a 1 to signify inversion if the 1'"'"'s count is greater than N/2 and to append the control bit as a 0 if the 1'"'"'s count is not greater than N/2, thereby forming a stored sector of N+1 bits; and

the erased page detector comprises;

a counter for counting the number of 1'"'"'s in the stored sector to determine a stored 1'"'"'s count,

a comparator for comparing the stored 1'"'"'s count with N/2 to provide a conditional output if the stored 1'"'"'s count is greater than N/2,

an inverter for inverting the stored sector to form an inverted stored sector if the 1'"'"'s count is not greater than N/2, and

a remover for removing the control bit to provide an output sector of N bits formed of the inverted stored sector if the 1'"'"'s count is not greater than N/2 and formed of the stored sector if the 1'"'"'s count is greater than N/2.

9. In a memory device including a memory having a plurality of nonvolatile memory cells for storing data, a method of controlling the memory comprising:

encoding user write data to generate encoded data;

while encoding the user write data, inserting an indicator in the user write data, wherein the indicator indicates whether or not the encoded data is in an erased state, wherein a first data is in the erased state if the first data is intended to erase a section of the memory in which the first data is to be stored;

storing the encoded data in the memory;

reading the encoded data from the memory; and

based on the encoded data not being in the erased state, decoding the encoded data read from the memory, to generate user read data,

wherein decoding the encoded data comprises

counting a number of 1'"'"'s in the encoded data read from the memory,

based on the counted number of 1'"'"'s in the encoded data being less than a threshold, determining that the encoded data is in the erased state,

wherein the user write data comprises code values having N number of data bits, where N is an integer, and

wherein the threshold is equal to N/2.

10. The method of claim, 9 wherein the decoding detects the indicator in the encoded data read from the memory.

11. In a memory device including a memory having a plurality of nonvolatile memory cells for storing data, a method of controlling the memory comprising:

encoding user write data to generate encoded data;

while encoding the user write data, appending a flag to the user write data, wherein the flag indicates whether or not the encoded data is in an erased state, wherein a first data is in the erased state if the first data is intended to erase a section of the memory in which the first data is to be stored;

storing the encoded data in the memory;

reading the encoded data from the memory; and

decoding the encoded data read from the memory, to generate user read data, wherein decoding the encoded data comprises detecting the flag in the user read data,

wherein the flag is a 2-bit flag, and

wherein “

10” and

“

01”

states of the 2-bit flag indicate that the encoded data is not in the erased state.

12. The method of claim 11, wherein:

encoding the user write data further comprises;

generating a cyclic redundancy code (CRC) value corresponding to the user write data, and

converting the CRC value to a converted CRC′

value to indicate a presence of a code word in the user write data; and

decoding the encoded data further comprises;

detecting the converted CRC′

value to sense the presence of the code word in the user write data, and

converting the converted CRC′

value to the CRC value.