Architecture for ultra-wideband radio
First Claim
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1. A transmitter, comprising:
- a sequence generator to generate and output a timing sequence; and
an output stage to generate an impulse radio signal using the timing sequence, wherein the impulse radio signal comprises a plurality of dual pulses spaced in time, wherein the output stage comprises a buffer to generate a first output and a second output, a delay line to delay the first output or the second output, and a multiplier to combine the delayed first output and the second output.
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Abstract
Provided are transmitter topology, receiver topology and methods for generating and transmitting a radio signal at a transmitter and detecting and processing a radio signal at a receiver. The radio signals are transmitted across a wireless interface using Ultra Wideband (UWB) pulses. A transmitted reference approach is utilized. The radio signal include pairs of UWB pulses with each pair of pulses separated by a fixed time delay. The two pulses are then combined to provide for improved noise immunity.
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17 Claims
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1. A transmitter, comprising:
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a sequence generator to generate and output a timing sequence; and an output stage to generate an impulse radio signal using the timing sequence, wherein the impulse radio signal comprises a plurality of dual pulses spaced in time, wherein the output stage comprises a buffer to generate a first output and a second output, a delay line to delay the first output or the second output, and a multiplier to combine the delayed first output and the second output. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for generating and transmitting a radio signal in a transmitter-receiver environment, comprising the steps of:
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generating a high-speed timing sequence; and generating an impulse radio signal using the high-speed timing sequence, wherein the radio signal comprises a plurality of dual pulses spaced in time, wherein the step of generating the impulse radio signal using the high-speed timing sequence comprises the steps of; generating a differential pair of sequences from the high-speed timing sequence, comprising a first differential sequence and a second differential sequence, delaying the first differential sequence, and multiplying the delayed first differential sequence and the second differential sequence. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification