Parallel correlator implementation using hybrid correlation in spread-spectrum communication

• US 8,351,486 B2
• Filed: 03/26/2009
• Issued: 01/08/2013
• Est. Priority Date: 09/15/2005
• Status: Active Grant

• Current Assignee: Maishi Electronic (Shanghai) Limited
• Original Assignee: Maishi Electronic (Shanghai) Limited
• Inventors: Cheng, MingQiang, Li, Shijie, Yu, Bo
• Primary Examiner(s): Liu, Shuwang
• Assistant Examiner(s): AHN, SUNG S
• Application Number:
  US12/411,538
• Publication Number:
  US 20090225816A1
• Time in Patent Office: 1,384 Days
• Field of Search: 375/147, 375/150, 375/152
• US Class Current: 375/147
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence

Abstract

An apparatus for processing spread spectrum signals is disclosed. The apparatus includes an intermediate frequency (IF) signal preprocessing unit, which includes a first set of multiply-accumulator (MAC) units and a second set of MAC units. The IF signal preprocessing unit generates a first and a second set of data streams using a digitized signal and a first and second local reference signals respectively. Each data stream is generated every predetermined time period, and each data stream includes pre-integration results generated at a predetermined rate.

Claims

1. An apparatus for processing spread spectrum signals, comprising:

an intermediate frequency (IF) signal preprocessing unit operable for generating a first and a second set of data streams using a digitized signal and a first and second local reference signals respectively, wherein each data stream is generated every predetermined time period, wherein each data stream includes pre-integration results generated at a predetermined rate, and wherein the IF signal preprocessing unit comprises;

a first set of multiply-accumulator (MAC) units, each MAC unit in the first set of MAC units is operable for generating the pre-integration results of one of the first set of data streams, wherein each pre-integration result is generated by multiplying each data point of the digitalized signal by a respective data point of the first local reference signal to produce multiplication results and summing the multiplication results within a data length;

a second set of MAC units, each MAC unit in the second set of MAC units is operable for generating the pre-integration results of one of the second set of data streams, wherein each pre-integration result is generated by multiplying each data point of the digitized signal by a respective data point of the second local reference signal to produce multiplication results and summing the multiplication results within the data length;

a code clock generator coupled to each MAC unit in the first set of MAC units and each MAC unit in the second set of MAC units, and operable for controlling the pre-integration results of each data stream to be generated at the same predetermined rate, wherein the predetermined rate is a function of a pseudorandom noise (PRN) code rate;

a plurality of block integrators in communication with the IF signal preprocessing unit, each block integrator is operable for receiving a data stream in the first and second set of data streams and a PRN code, and performing a first predetermined number of partial correlations based on the data stream and the pseudorandom noise code; and

a plurality of sets of shift registers, each set of shift registers is in communication with the IF signal preprocessing unit and at least one block integrator of the plurality of block integrators,

wherein each set of shift registers stores a predetermined number of pre-integration results of a data stream in the first and second set of data streams and shifts the predetermined number of pre-integration results after a pre-integration result of the data stream is generated by the intermediate frequency signal preprocessing unit, and wherein for each shift of a set of shift registers, each block integrator performs a second predetermined number of partial correlations, wherein each partial correlation is performed based on the predetermined number of pre-integration results in the set of shift registers and a shifted segment of the PRN code, and the segment of the PRN code is shifted by a predetermined position.

2. The apparatus of claim 1, wherein the predetermined time period is a function of the duration of half a PRN code chip.

3. The apparatus of claim 1, further comprising:

a code generator coupled to the code clock generator and for generating a plurality of PRN codes.

4. The apparatus of claim 1, wherein each block integrator comprises a parallel multiply-accumulator (MAC) unit for performing the partial correlation, wherein the partial correlation is obtained by performing multiplication and addition calculations based on the predetermined number of the pre-integration results of the data stream and a corresponding segment of the PRN code.

5. The apparatus of claim 1, further comprising:

a control logic in communication with the plurality of block integrators and a storage unit for reading a previous partial correlation result from the storage unit, adding a current partial correlation result to the previous partial correlation result to produce a modified partial correlation result, and writing the modified partial correlation result back into the storage unit, wherein the previous partial correlation result and the current partial correlation result being a portion of a complete correlation result.

6. The apparatus of claim 1, wherein after a plurality of shifting of the set of shift registers, each block integrator performs the first predetermined number of partial correlations.

7. The apparatus of claim 1, further comprising:

an asynchronous interface coupled between the intermediate frequency signal preprocessing unit and the plurality of sets of shift registers, the asynchronous interface being capable of separating the sampling frequency and a working frequency, wherein each partial correlation being performed at the working frequency.

8. A method for processing spread spectrum signals, comprising:

receiving a digitized signal and a local reference signal;

multiplying each data point of the digitalized signal by each respective data point of the local reference signal to produce multiplication results;

adding the multiplication results to produce pre-integration results within a data length;

generating a plurality of data streams by an intermediate frequency (IF) signal preprocessing unit using the digitized signal and the local reference signal, wherein each data stream is generated every predetermined time period and each data stream includes the pre-integration results generated by the IF signal preprocessing unit at the same predetermined rate, and wherein the predetermined rate is a function of a pseudorandom noise (PRN) code rate;

receiving a data stream from the plurality of data streams and a PRN code at each of a plurality of block integrators;

performing a first predetermined number of partial correlations at each block integrator based on the data stream and the PRN code to obtain a predetermined number of partial correlation results; and

computing a predetermined number of complete correction results based on the first predetermined number of partial correlation results,

wherein the step of performing the first predetermined number of partial correlations comprises the steps of;

a) obtaining a partial correlation by performing multiplication and addition calculations based on a predetermined number of pre-integration results of the data stream and a segment of the pseudorandom noise code;

b) shifting the segment of the pseudorandom noise code by a predetermined position;

c) repeating step a) and b) until a second predetermined number of partial correlations are achieved in each block integrator;

d) shifting the predetermined number of pre-integration results received by each block integrator after a pre-integration result of the data stream is generated; and

e) repeating step a) through d) until the first predetermined number of partial correlations are achieved in each block integrator.

9. The method of claim 8, the data length being a function of a PRN code chip length.

10. The method of claim 8, wherein the predetermined time period is a function of the duration of half a PRN code chip.

11. The method of claim 8, wherein the predetermined position is a phase shift based on a PRN code chip.