Method and system for specualtively sending processor-issued store operations to a store queue with full signal asserted
First Claim
1. In a data processing system with a processor chip that includes a processor core and a store queue with multiple entries, a method for speculatively issuing a store operation from the processor core to the store queue, said method comprising:
- determining when the store queue is full, wherein said store queue has multiple entries with at least one entry capable of concurrently holding multiple store operations, and the store queue is “
full”
when all entries of the store queue currently holds at least one store operation issued from the processor core; and
while said store queue is full, speculatively issuing a next store operation to the store queue as a first speculative store operation, wherein the next store operation is issued as a normal, non-speculative store operation when said store queue is not full;
wherein the at least one entry of the store queue is designed to gather multiple store operations when the store operations target portions of the same cache line; and
wherein said first speculative store operation is scheduled for re-issue to the store queue if (a) the first speculative store operation is not gathered by one of the entries within the store queue, and (b) no entry within the store queue becomes empty before the first speculative store operations arrives at the store queue.
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Accused Products
Abstract
A method and processor chip design for enabling a processor core to continue sending store operations speculatively to the store queue after the core receives indication that the store queue is full. The processor core is configured with speculative store logic that enables the processor core to continue issuing store operations while the store queue full signal is asserted. A copy of the speculatively issued store operation is placed within a speculative store buffer. The core waits for a signal from the store queue indicating the store operation was accepted into the store queue. When the speculatively-issued store operation is accepted within the store queue, the copy is discarded from the buffer. However, when the store operation is rejected, the speculative store logic re-issues the store operation ahead of normal store operations.
32 Citations
28 Claims
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1. In a data processing system with a processor chip that includes a processor core and a store queue with multiple entries, a method for speculatively issuing a store operation from the processor core to the store queue, said method comprising:
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determining when the store queue is full, wherein said store queue has multiple entries with at least one entry capable of concurrently holding multiple store operations, and the store queue is “
full”
when all entries of the store queue currently holds at least one store operation issued from the processor core; andwhile said store queue is full, speculatively issuing a next store operation to the store queue as a first speculative store operation, wherein the next store operation is issued as a normal, non-speculative store operation when said store queue is not full; wherein the at least one entry of the store queue is designed to gather multiple store operations when the store operations target portions of the same cache line; and wherein said first speculative store operation is scheduled for re-issue to the store queue if (a) the first speculative store operation is not gathered by one of the entries within the store queue, and (b) no entry within the store queue becomes empty before the first speculative store operations arrives at the store queue. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A processor chip for utilization within a data processing system, said processor chip comprising:
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a store queue having multiple entries, each entry capable of gathering multiple processor issued store operations targeting the same address, and the store queue is “
full”
when all entries of the store queue currently holds at least one store operation issued from the processor core;tracking logic for determining when all the entries within the store queue have been allocated to at least one processor-issued store operation, indicating that the store queue is full; and a processor core having normal logic for issuing store operations as a normal store when the store queue is not full and speculative store logic for speculatively issuing store operations when the store queue is full; wherein a speculatively issued store operation is scheduled for re-issue to the store queue if the speculatively issued store operation is not gathered by one of the entries within the store queue, and if no entry within the store queue becomes empty before the speculatively issued store operations arrives at the store queue. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. A data processing system comprising:
a processor chip that includes; a store queue having multiple entries, each entry capable of gathering multiple processor issued store operations targeting a same cache line address, and the store queue is “
full”
when all entries of the store queue currently holds at least one store operation issued from the processor core;tracking logic for determining when all the entries within the store queue have been allocated to at least one processor-issued store operation, indicating that the store queue is full; and a processor core having normal logic for issuing store operations as a normal store when the store queue is not full and speculative store logic for speculatively issuing store operations when the store queue is full; and a memory hierarchy coupled to said processor chip; wherein a speculatively issued store operation is scheduled for re-issue to the store queue if the speculatively issued store operation is not gathered by one of the entries within the store queue, and if no entry within the store queue becomes empty before the speculatively issued store operations arrives at the store queue. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
Specification