Techniques to perform forward error correction for an electrical backplane

• US 8,352,828 B2
• Filed: 01/11/2012
• Issued: 01/08/2013
• Est. Priority Date: 01/04/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ganga, Ilango S., Chang, Luke, Belogolovy, Andrey, Ovchinnikov, Andrei
• Primary Examiner(s): ABRAHAM, ESAW T
• Application Number:
  US13/348,341
• Publication Number:
  US 20120110421A1
• Time in Patent Office: 363 Days
• Field of Search: 714/752, 714/775, 714/789, 714/798
• US Class Current: 714/752
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: H03M 13/33 Synchronisation based on error coding or decoding
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence
• CPC Class Codes: H03M 13/6312 Error control coding in combination with data compression
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/0042 Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0058 Block-coded modulation
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 1/0072 Error control for data other than payload data, e.g. control data
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/041 using special codes as synchronising signal
• CPC Class Codes: Y02D 30/00 Reducing energy consumption in communication networks

Abstract

Techniques to perform forward error correction for an electrical backplane are described. An apparatus may include a physical layer unit having a forward error correction sublayer to perform forward error correction.

Claims

1. An apparatus, comprising:

circuitry of a forward error correction (FEC) sublayer to perform forward error correction, the FEC sublayer coupled to a physical coding sublayer and a physical medium attachment (PMA) sublayer, the FEC sublayer comprising an encoder having;

a reverse gearbox;

a compressor coupled to said reverse gearbox;

a selector coupled to said compressor;

a parity generator coupled to said compressor;

a multiplexer coupled to said compressor, selector and said parity generator;

a scrambler to couple to said multiplexer; and

a pseudo-noise generator to couple to said scrambler.

2. The apparatus of claim 1, wherein the FEC sublayer circuitry comprises a processor.

3. The apparatus of claim 1, wherein the FEC sublayer comprises a plurality of hardware components forming a part of a hardware physical layer unit.

4. The apparatus of claim 1, wherein the PCS block has 66 bits including the two bit synchronization header.

5. The apparatus of claim 1, comprising a forward error correction decoder and block synchronizer to comprise:

a descrambler;

a pseudo-noise generator to couple to said descrambler;

a synchronizer to couple to said descrambler;

a decoder to couple to said synchronizer;

an error monitor to couple to said decoder; and

a reconstructor to couple to said decoder.