Semiconductor chip assembly with bump/base/ledge heat spreader, dual adhesives and cavity in bump

• US 8,354,688 B2
• Filed: 12/24/2011
• Issued: 01/15/2013
• Est. Priority Date: 03/25/2008
• Status: Expired due to Fees

• Current Assignee: Bridge Semiconductor Corporation
• Original Assignee: Bridge Semiconductor Corporation
• Inventors: Lin, Charles W. C., Wang, Chia-Chung
• Primary Examiner(s): Cao, Phat X
• Application Number:
  US13/337,054
• Publication Number:
  US 20120091493A1
• Time in Patent Office: 388 Days
• Field of Search: 257/99, 257/707, 257/E33.058, 438/25, 438/118
• US Class Current: 257/99
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/2929 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29339 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/8385 using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
• CPC Class Codes: H01L 2224/85205 Ultrasonic bonding
• CPC Class Codes: H01L 2224/8592 Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 33/483 : Containers
• CPC Class Codes: H01L 33/642 : characterized by the shape
• CPC Class Codes: H05K 1/021 : Components thermally connected to metal substrates or heat-sinks by insert mounting
• CPC Class Codes: H05K 2201/0352 : Differences between the conductors of different layers of a multilayer
• CPC Class Codes: H05K 2201/0355 : Metal foils
• CPC Class Codes: H05K 2201/10106 : Light emitting diode [LED]
• CPC Class Codes: H05K 2203/049 : Wire bonding
• CPC Class Codes: H05K 2203/063 : of preperforated insulating layer
• CPC Class Codes: H05K 3/4084 : by deforming at least one of the conductive layers

Abstract

A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace and dual adhesives. The heat spreader includes a bump, a base and a ledge. The conductive trace includes a pad and a terminal. The semiconductor device is mounted on the bump in a cavity in the bump, is electrically connected to the conductive trace and is thermally connected to the heat spreader. The bump extends into an opening in the first adhesive and is aligned with and spaced from an opening in the second adhesive. The base and the ledge extend laterally from the bump. The first adhesive is sandwiched between the base and the ledge, the second adhesive is sandwiched between the conductive trace and the ledge and the ledge is sandwiched between the adhesives. The conductive trace is located outside the cavity and provides signal routing between the pad and the terminal.

Claims

1. A semiconductor chip assembly, comprising:

a semiconductor device;

a first adhesive that includes a first opening;

a second adhesive that includes a second opening;

a conductive trace that includes a pad and a terminal; and

a heat spreader that includes a bump, a base and a ledge, wherein (i) the bump is adjacent to the base and the ledge, is integral with the ledge, extends from the base in a first vertical direction and extends from the ledge in a second vertical direction opposite the first vertical direction, (ii) the base covers the bump in the second vertical direction and extends laterally from the bump in lateral directions orthogonal to the vertical directions, (iii) the ledge extends laterally from the bump and is spaced from the base, and (iv) a cavity in the bump faces in the first vertical direction, is covered by the bump in the second vertical direction and is spaced from the base by the bump;

wherein the semiconductor device is mounted on the bump, extends into the cavity, is electrically connected to the pad and thereby electrically connected to the terminal, and is thermally connected to the bump and thereby thermally connected to the base;

wherein the first adhesive contacts the bump, the base and the ledge, is sandwiched between the base and the ledge and extends laterally from the bump to or beyond the terminal;

wherein the second adhesive is spaced from the bump, is sandwiched between the conductive trace and the ledge, extends beyond the ledge and the first adhesive in the first vertical direction and extends beyond the conductive trace in the second vertical direction;

wherein the conductive trace is located outside the cavity and beyond the ledge in the first vertical direction;

wherein the bump extends into the first opening, is aligned with and spaced from the second opening and covers the semiconductor device in the second vertical direction;

wherein the ledge is sandwiched between the adhesives and covers the conductive trace in the second vertical direction; and

wherein the cavity extends into the first opening and is aligned with and spaced from the second opening.

2. The assembly of claim 1, wherein the semiconductor device is an LED chip.

3. The assembly of claim 1, wherein the semiconductor device is located within the cavity, is electrically connected to the pad using a wire bond that extends from the cavity through the second opening to the pad and is thermally connected to the bump using a die attach that is located within the cavity.

4. The assembly of claim 1, wherein the first adhesive laterally covers and surrounds and conformally coats a sidewall of the bump.

5. The assembly of claim 1, wherein the first adhesive extends to peripheral edges of the assembly.

6. The assembly of claim 1, wherein the first adhesive extends laterally from the bump beyond the conductive trace.

7. The assembly of claim 1, wherein the second adhesive is adhesive tape.

8. The assembly of claim 1, wherein the second adhesive extends to peripheral edges of the assembly.

9. The assembly of claim 1, wherein the bump is coplanar with the first adhesive at the base and at the ledge.

10. The assembly of claim 1, wherein the bump is adjacent to the base at a first bent corner and is adjacent to the ledge at a second bent corner.

11. The assembly of claim 1, wherein the bump has an irregular thickness characteristic of stamping.

12. The assembly of claim 1, wherein the cavity extends across most of the bump in the vertical and lateral directions.

13. The assembly of claim 1, wherein the base has a first thickness where it is adjacent to the bump, a second thickness where it is spaced from the bump by the first adhesive that is larger than the first thickness and a flat surface that faces in the second vertical direction.

14. The assembly of claim 1, wherein the base covers the bump, the ledge, the conductive trace and the adhesives in the second vertical direction and extends to peripheral edges of the assembly.

15. The assembly of claim 1, wherein the ledge covers the second adhesive in the second vertical direction and extends to peripheral edges of the assembly.

16. The assembly of claim 1, wherein the pad and the terminal have the same thickness and are coplanar with one another at a surface that faces in the first vertical direction.

17. The assembly of claim 1, wherein a first dielectric layer contacts and is sandwiched between the base and the first adhesive and is spaced from the bump, the ledge and the second adhesive, and the bump and the first adhesive extend through a first aperture in the first dielectric layer.

18. The assembly of claim 1, wherein a second dielectric layer contacts and is sandwiched between the conductive trace and the second adhesive and is spaced from the bump, the base, the ledge and the first adhesive, and the bump is aligned with and spaced from a second aperture in the second dielectric layer.

19. The assembly of claim 1, wherein the bump, the base, the ledge, the pad and the terminal are primarily copper.

20. The assembly of claim 1, wherein the heat spreader includes a copper core shared by the bump, the base and the ledge and the conductive trace includes a copper core shared by the pad and the terminal.

21. A semiconductor chip assembly, comprising:

a semiconductor device;

a first adhesive that includes a first opening;

a second adhesive that includes a second opening;

a first substrate that includes a first dielectric layer, wherein a first aperture extends through the first substrate;

a second substrate that includes a second dielectric layer, wherein a second aperture extends through the second substrate;

a conductive trace that includes a pad and a terminal; and

a heat spreader that includes a bump, a base and a ledge, wherein (i) the bump is adjacent to the base and the ledge, is integral with the ledge, extends from the base in a first vertical direction and extends from the ledge in a second vertical direction opposite the first vertical direction, (ii) the base covers the bump in the second vertical direction and extends laterally from the bump in lateral directions orthogonal to the vertical directions, (iii) the ledge extends laterally from the bump and is spaced from the base, and (iv) a cavity in the bump faces in the first vertical direction, is covered by the bump in the second vertical direction and is spaced from the base by the bump;

wherein the semiconductor device is mounted on the bump, extends into the cavity, is electrically connected to the pad and thereby electrically connected to the terminal, and is thermally connected to the bump and thereby thermally connected to the base;

wherein the first adhesive contacts the bump, the base, the ledge and the first dielectric layer, is spaced from the second adhesive and the second dielectric layer, is sandwiched between the bump and the first dielectric layer, between the ledge and the first dielectric layer and between the base and the ledge, extends through the first aperture and extends laterally from the bump to or beyond the terminal;

wherein the second adhesive is spaced from the bump and the conductive trace, is sandwiched between the ledge and the second dielectric layer, extends beyond the ledge, the first adhesive and the first dielectric layer in the first vertical direction and extends beyond the conductive trace and the second dielectric layer in the second vertical direction;

wherein the first dielectric layer contacts and is sandwiched between the base and the first adhesive and is spaced from the bump, the ledge and the second dielectric layer;

wherein the second dielectric layer contacts and is sandwiched between the conductive trace and the second adhesive and is spaced from the bump, the base and the ledge;

wherein the conductive trace is located outside the cavity and beyond the ledge and the adhesives in the first vertical direction;

wherein the bump extends into the first opening, extends through the first aperture, is aligned with and spaced from the second opening and the second aperture and covers the semiconductor device in the second vertical direction;

wherein the base extends beyond the adhesives and the dielectric layers in the second vertical direction;

wherein the ledge is sandwiched between the adhesives and covers the conductive trace, the second adhesive and the second dielectric layer in the second vertical direction;

wherein the cavity extends into the first opening and is aligned with and spaced from the second opening and the second aperture; and

wherein the base, the ledge, the adhesives and the dielectric layers extend to peripheral edges of the assembly.

22. The assembly of claim 21, wherein the semiconductor device is an LED chip.

23. The assembly of claim 21, wherein the semiconductor device is located within the cavity, is electrically connected to the pad using a wire bond that extends from the cavity through the second opening and the second aperture to the pad and is thermally connected to the bump using a die attach that is located within the cavity.

24. The assembly of claim 21, wherein the first adhesive laterally covers and surrounds and conformally coats a sidewall of the bump and the second adhesive is adhesive tape.

25. The assembly of claim 21, wherein the bump is coplanar with the first adhesive at the base and at the ledge.

26. The assembly of claim 21, wherein the bump is adjacent to the base at a first bent corner and is adjacent to the ledge at a second bent corner.

27. The assembly of claim 21, wherein the bump has an irregular thickness characteristic of stamping.

28. The assembly of claim 21, wherein the bump provides a recessed die paddle and a reflector for the semiconductor device.

29. The assembly of claim 21, wherein the cavity extends across most of the bump in the vertical and lateral directions.

30. The assembly of claim 21, wherein the base has a first thickness where it is adjacent to the bump, a second thickness where it is adjacent to the first dielectric layer that is larger than the first thickness and a flat surface that faces in the second vertical direction.

31. The assembly of claim 21, wherein the base covers the bump, the ledge, the conductive trace, the adhesives and the dielectric layers in the second vertical direction.

32. The assembly of claim 21, wherein the ledge covers the first dielectric layer in the first vertical direction.

33. The assembly of claim 21, wherein the bump and the ledge in combination cover the base in the first vertical direction and the base covers the bump and the ledge in the second vertical direction.

34. The assembly of claim 21, wherein the bump and the ledge in combination cover the base, the first adhesive and the first dielectric layer in the first vertical direction and the base covers the bump, the ledge, the conductive trace, the adhesives and the dielectric layers in the second vertical direction.

35. The assembly of claim 21, wherein the first substrate is a single-sided copper clad laminate that includes the first dielectric layer and the base where it is adjacent to the first dielectric layer and the second substrate is single-sided copper clad laminate that includes the conductive trace and the second dielectric layer.

36. The assembly of claim 21, wherein the pad and the terminal have the same thickness and are coplanar with one another at a surface that faces in the first vertical direction.

37. The assembly of claim 21, wherein a solder mask contacts and is sandwiched between the ledge and the second adhesive, is spaced from the bump, the base, the conductive trace, the first adhesive and the dielectric layers and includes a window that defines a reflective surface finish for the bump at the cavity, the bump is aligned with the window and the conductive trace has a different surface finish than the reflective surface finish.

38. The assembly of claim 21, wherein an encapsulant contacts the semiconductor device and the bump in the cavity and covers the semiconductor device in the first vertical direction.

39. The assembly of claim 21, wherein the bump, the base, the ledge, the pad and the terminal are primarily copper.

40. The assembly of claim 21, wherein the heat spreader includes a copper core shared by the bump, the base and the ledge and the conductive trace includes a copper core shared by the pad and the terminal.

41. A semiconductor chip assembly, comprising:

a semiconductor device;

a first adhesive that includes a first opening;

a second adhesive that includes a second opening;

a first substrate that includes a first dielectric layer, wherein a first aperture extends through the first substrate;

a second substrate that includes a second dielectric layer, wherein a second aperture extends through the second substrate;

a conductive trace that includes a pad and a terminal; and

a heat spreader that includes a bump, a base and a ledge, wherein (i) the bump is adjacent to the base at a first bent corner, is adjacent to the ledge at a second bent corner, is integral with the ledge, extends from the base in a first vertical direction and extends from the ledge in a second vertical direction opposite the first vertical direction, (ii) the base covers the bump in the second vertical direction and extends laterally from the bump in lateral directions orthogonal to the vertical directions, (iii) the ledge extends laterally from the bump opposite the base and is spaced from the base by the bump, and (iv) a cavity in the bump faces in the first vertical direction, is covered by the bump in the second vertical direction, is spaced from the base by the bump and has an entrance at the ledge;

wherein the semiconductor device is mounted on the bump, extends into the cavity, is electrically connected to the pad and thereby electrically connected to the terminal, and is thermally connected to the bump and thereby thermally connected to the base;

wherein the first adhesive contacts the bump, the base, the ledge and the first dielectric layer, is spaced from the second adhesive and the second dielectric layer, is sandwiched between the bump and the first dielectric layer, between the ledge and the first dielectric layer and between the base and the ledge, extends through the first aperture and extends laterally from the bump to or beyond the terminal;

wherein the second adhesive contacts the second dielectric layer, is spaced from the bump, the base, the conductive trace and the first adhesive, is sandwiched between the ledge and the second dielectric layer, extends beyond the ledge, the first adhesive and the first dielectric layer in the first vertical direction and extends beyond the conductive trace and the second dielectric layer in the second vertical direction;

wherein the first dielectric layer contacts and is sandwiched between the base and the first adhesive and is spaced from the bump, the ledge and the second dielectric layer;

wherein the second dielectric layer contacts and is sandwiched between the conductive trace and the second adhesive and is spaced from the bump, the base and the ledge;

wherein the conductive trace is located outside the cavity and beyond the bump, the ledge, the adhesives and the dielectric layers in the first vertical direction;

wherein the bump extends into the first opening, extends through the first aperture, is aligned with and spaced from the second opening and the second aperture, covers the semiconductor device in the second vertical direction and provides a recessed die paddle and a reflector for the semiconductor device;

wherein the base covers the bump, the ledge, the conductive trace, the adhesives and the dielectric layers in the second vertical direction;

wherein the ledge is sandwiched between the adhesives and covers the conductive trace, the second adhesive and the second dielectric layer in the second vertical direction;

wherein the cavity extends into the first opening and the first aperture and is aligned with and spaced from the second opening and the second aperture;

wherein the bump and the ledge in combination cover the base, the first adhesive and the first dielectric layer in the first vertical direction; and

wherein the base, the ledge, the adhesives and the dielectric layers extend to peripheral edges of the assembly.

42. The assembly of claim 41, wherein the semiconductor device is an LED chip, is located within the cavity, is electrically connected to the pad using a wire bond that extends from the cavity through the second opening and the second aperture to the pad and is thermally connected to the bump using a die attach that is located within the cavity.

43. The assembly of claim 41, wherein the first adhesive laterally covers and surrounds and conformally coats a sidewall of the bump and the second adhesive is adhesive tape.

44. The assembly of claim 41, wherein the bump is coplanar with the first adhesive at the base and at the ledge and the base has a first thickness where it is adjacent to the bump, a second thickness where it is adjacent to the first dielectric layer that is larger than the first thickness and a flat surface that faces in the second vertical direction.

45. The assembly of claim 41, wherein the cavity extends across most of the bump in the vertical and lateral directions.

46. The assembly of claim 41, wherein the first substrate is a single-sided copper clad laminate that includes the first dielectric layer and the base where it is adjacent to the first dielectric layer and the second substrate is single-sided copper clad laminate that includes the conductive trace and the second dielectric layer.

47. The assembly of claim 41, wherein a solder mask contacts and is sandwiched between the ledge and the second adhesive, is spaced from the bump, the base, the conductive trace, the first adhesive and the dielectric layers and includes a window that defines a reflective surface finish for the bump, the reflective surface finish extends from the bump within the cavity to the ledge outside the cavity, the bump is aligned with the window and the conductive trace has a different surface finish than the reflective surface finish.

48. The assembly of claim 41, wherein an encapsulant contacts the semiconductor device and the bump in the cavity and covers the semiconductor device in the first vertical direction.

49. The assembly of claim 48, wherein the encapsulant is a color-shifting encapsulant that includes silicone and phosphor.

50. The assembly of claim 41, wherein the bump, the base, the ledge, the pad and the terminal are primarily copper, the heat spreader includes a copper core shared by the bump, the base and the ledge and the conductive trace includes a copper core shared by the pad and the terminal.