Solid-state pinch off thyristor circuits

• US 8,354,690 B2
• Filed: 08/31/2009
• Issued: 01/15/2013
• Est. Priority Date: 08/31/2009
• Status: Active Grant

• Current Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Callanan, Robert J., Ryu, Sei-Hyung, Zhang, Qingchun
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US12/550,574
• Publication Number:
  US 20110049561A1
• Time in Patent Office: 1,233 Days
• Field of Search: 257/121, 257/124, 257/119, 257/147, 257/157, 257/E29.211, 257/E29.221, 257/E29.212, 257/107
• US Class Current: 257/121
• CPC Class Codes: H01L 29/1602 Diamond
• CPC Class Codes: H01L 29/1608 Silicon carbide
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/745 with turn-off by field effect
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure

Abstract

Provided is a semiconductor bistable switching device that includes a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode. The device also includes a transistor portion formed on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain coupled to the cathode of the thyristor portion.

Claims

1. A semiconductor bistable switching device comprising:

a thyristor portion including an anode layer, a drift layer, a gate layer and a cathode layer, the gate layer is operable to receive a gate trigger current that, when the anode layer is positively biased relative to the cathode layer, causes the thyristor portion to latch into a conducting mode between the anode and the cathode; and

a transistor portion on the thyristor portion, the transistor portion including a source, a drain and a transistor gate, the drain is coupled to the cathode of the thyristor portion,

wherein the thyristor portion and the transistor portion are integrated into a monolithic device.

2. The device according to claim 1, wherein the anode layer of the thyristor portion is operable as a switching device anode and wherein the source of the transistor portion is operable as a switching device cathode.

3. The device according to claim 1, wherein the transistor gate is operable to receive a turn off signal that causes a current conducting channel between the source and the drain to increase in resistance.

4. The device according to claim 1, wherein the transistor portion comprises a junction field effect transistor (JFET) that is configured to pinch off current flow from the source to the drain responsive to a voltage applied to the transistor gate.

5. The device according to claim 1, wherein the thyristor portion comprises a gate turn off thyristor (GTO).

6. The device according to claim 1, wherein the anode layer, drift layer, gate layer and cathode layer are disposed in a silicon carbide (SiC) layer.

7. The device according to claim 1, further comprising:

a first external diode including a first anode that is coupled to the gate layer and a first cathode; and

a second external diode including a second anode that is coupled to the first cathode and a second cathode that is coupled to the drain.

8. The device according to claim 1, wherein the anode layer, the drift layer, the gate layer and the cathode layer, respectively comprise PNPN-type layers.

9. An integrated semiconductor switching device comprising:

a thyristor anode layer having a first conductivity type;

a thyristor drift layer on the anode semiconductor layer, the drift layer having a second conductivity type that is different from the first conductivity type;

a thyristor gate layer on the drift layer, the gate layer having a third conductivity type that is different from the second conductivity type;

a patterned thyristor cathode layer on the gate layer, the patterned cathode layer having a fourth conductivity type that is different from the third conductivity type;

a patterned transistor drain layer on the patterned thyristor cathode layer;

a patterned transistor source layer on the patterned transistor drain layer; and

a patterned transistor gate layer adjacent a current channel formed by at least one of the patterned transistor drain layer or the patterned transistor source layer.

10. The device according to claim 9, wherein the patterned transistor drain layer, the patterned transistor source layer and the patterned transistor gate layer comprise a junction field effect transistor (JFET).

11. The device according to claim 9,

wherein the thyristor anode layer comprises a p-type SiC layer,

wherein the thyristor drift layer comprises a n-type SiC layer;

wherein the thyristor gate layer comprises a p-type SiC layer; and

wherein the patterned thyristor cathode layer comprises a n-type SiC layer.

12. The device according to claim 9,

wherein the thyristor anode layer comprises a n-type SiC layer;

wherein the thyristor drift layer comprises a p-type SiC layer;

wherein the thyristor gate layer comprises a n-type SiC layer; and

wherein the patterned thyristor cathode layer comprises a p-type SiC layer.

13. A semiconductor bistable switching circuit comprising:

a first node corresponding to a circuit anode and electrically coupled to a thyristor portion anode;

a second node corresponding to a circuit turn on gate and electrically coupled to a thyristor portion gate;

a third node corresponding to a circuit cathode and electrically coupled to a transistor portion drain, the transistor portion including a transistor portion source that is electrically coupled to a thyristor portion cathode; and

a fourth node corresponding to a circuit turn off gate and electrically coupled to a transistor portion gate,

wherein the thyristor portion and the transistor portion comprise a monolithic device.

14. The circuit according to claim 13, further comprising:

a first semiconductor diode including a first cathode and a first anode that is electrically coupled to the second node; and

a second semiconductor diode including a second anode that is electrically coupled to the first cathode and a second cathode that is electrically coupled to the third node,

wherein a voltage level at the second node is clamped to a voltage that corresponds to the voltage across the first semiconductor diode and the second semiconductor diode when the circuit is in a conducting state.

15. The circuit according to claim 13, wherein the circuit is turned on from a non-conducting state between the first and third nodes to a conducting state between the first and third nodes by forward biasing the first node relative to the third node and providing a momentary bias to the second node relative to the third node.

16. The circuit according to claim 13, wherein the circuit is turned off from a conducting state between the first and third nodes to a non-conducting state between the first and third nodes by supplying a current to the fourth node to cause a conducting channel in the transistor portion to have increased resistance that inhibits current flow therethrough.