Method of fabricating semiconductor device

• US 8,354,713 B2
• Filed: 05/13/2011
• Issued: 01/15/2013
• Est. Priority Date: 08/28/1997
• Status: Expired due to Fees

• Current Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Original Assignee: Hitachi ULSI Systems Company Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Numazawa, Sumito, Nakazawa, Yoshito, Kobayashi, Masayoshi, Kudo, Satoshi, Imai, Yasuo, Kubo, Sakae, Shigematsu, Takashi, Ohnishi, Akihiro, Uesawa, Kozo, Oishi, Kentaro
• Primary Examiner(s): Mandala, Michelle
• Assistant Examiner(s): WHITE, SHAKA SHAKAR
• Application Number:
  US13/107,542
• Publication Number:
  US 20110215398A1
• Time in Patent Office: 613 Days
• Field of Search: 257/E29.201, 257/E21.419
• US Class Current: 257/330
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0869 Shape cell layout H01L29/0696
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.

Claims

1. A semiconductor device including a MISFET, comprising:

a semiconductor substrate having a main surface and a back surface,

the semiconductor substrate including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, opposite to the first conductivity type, formed over the first semiconductor region and a third semiconductor region of the first conductivity type formed over the second semiconductor region;

a first trench formed in the semiconductor substrate,

a side surface of the first trench including a first portion and a second portion arranged near the main surface rather than the first portion such that the second portion has a sloping shape rather than the first portion;

a gate insulating film of the MISFET formed on the first trench and being in contact with the first semiconductor region, the second semiconductor region and the third semiconductor region such that an upper surface of the gate insulating film is arranged at a position lower than the second portion;

a gate electrode of the MISFET formed in the first trench such that an upper surface of the gate electrode is arranged at a position lower than the second portion;

a first insulating film has a lower surface extending over the upper surface of the gate insulating film, the upper surface of the gate electrode, the second portion and the main surface;

a second insulating film formed over an upper surface of the first insulating film,

the second insulating film having an opening exposing a side surface of the first insulating film; and

a conductive film formed over the second insulating film in self-alignment with the second insulating film and the side surface of the first insulating film,

the conductive film electrically connected to the second semiconductor region and the third semiconductor region through the opening,

wherein the third semiconductor region is serving as a source region of the MISFET,

wherein the second semiconductor region is serving as a channel forming region of the MISFET,

wherein the first semiconductor region is serving as a drain region of the MISFET.

2. The semiconductor device according to claim 1,

wherein the side surface of the first trench further includes a third portion arranged below the first portion such that the third portion has a sloping shape rather than first portion.

3. The semiconductor device according to claim 1,

wherein the first insulating film comprises a silicon oxide film, the second insulating film comprises a BPSG film.

4. The semiconductor device according to claim 1, further comprising:

a second trench formed in the semiconductor substrate and at a gate lead-out region of the main surface; and

a gate lead-out electrode formed in the second trench and outside the second trench,

the gate lead-out electrode formed integrally with the gate electrode of the MISFET,

the second insulating film and the first insulating film extending over the gate lead-out electrode positioned outside the second trench.

9. The semiconductor device according to claim 1,

wherein the gate electrode and the gate insulating film are not formed on the second portion.

5. A semiconductor device including a MISFET with a trench gate structure, comprising:

a semiconductor substrate having a main surface and a back surface,

the semiconductor substrate including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, opposite to the first conductivity type, formed over the first semiconductor region and a third semiconductor region of the first conductivity type formed over the second semiconductor region;

a first trench formed in the semiconductor substrate,

a side surface of the first trench including a first portion and a second portion arranged near the main surface rather than the first portion such that the second portion has a sloping shape rather than the first portion;

a gate insulating film of the MISFET formed on the first trench such that an upper surface of the gate insulating film is arranged at a position lower than the second portion;

a gate electrode of the MISFET formed in the first trench such that an upper surface of the gate electrode is arranged at a position lower than the second portion;

a first insulating film extending over the upper surface of the gate insulating film, the upper surface of the gate electrode, the second portion and the main surface;

a second insulating film formed over an upper surface of the first insulating film,

the second insulating film having an opening exposing a side surface of the first insulating film; and

a conductive film formed over the second insulating film in self-alignment with the second insulating film and the side surface of the first insulating film,

the conductive film electrically connected to the second semiconductor region and the third semiconductor region through the opening,

wherein the third semiconductor region is serving as a source region of the MISFET,

wherein the second semiconductor region is serving as a channel forming region of the MISFET,

wherein the first semiconductor region is serving as a drain region of the MISFET.

6. The semiconductor device according to claim 5,

wherein the side surface of the first trench further includes a third portion arranged below the first portion such that the third portion has a sloping shape rather than first portion.

7. The semiconductor device according to claim 5,

wherein the first insulating film comprises a silicon oxide film, the second insulating film comprises a BPSG film.

8. The semiconductor device according to claim 5, further comprising:

a second trench formed in the semiconductor substrate and at a gate lead-out region of the main surface; and

a gate lead-out electrode formed in the second trench and outside the second trench,

the gate lead-out electrode formed integrally with the gate electrode of the MISFET,

the second insulating film and the first insulating film extending over the gate lead-out electrode positioned outside the second trench.

10. The semiconductor device according to claim 5,

wherein the gate electrode and the gate insulating film are not formed on the second portion.