Apparatus and method for hardening latches in SOI CMOS devices

• US 8,354,858 B2
• Filed: 01/08/2011
• Issued: 01/15/2013
• Est. Priority Date: 09/19/2007
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cannon, Ethan H., KleinOsowski, AJ, Muller, K. Paul, Ning, Tak H., Oldiges, Philip J., Sigal, Leon J., Warnock, James D., Wendel, Dieter
• Primary Examiner(s): ISLA RODAS, RICHARD
• Application Number:
  US12/987,106
• Publication Number:
  US 20110102042A1
• Time in Patent Office: 738 Days
• Field of Search: 327/211, 257/921
• US Class Current: 324/762.09
• CPC Class Codes: H03K 3/0375 provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356156 with synchronous operation

Abstract

A method of determining one or more transistors within a particular circuit to be respectively replaced with a hardened transistor includes: identifying, as not requiring hardening, one or more transistors; identifying, as candidates for hardening, each transistor in the circuit not previously identified as not requiring hardening; and employing the hardened transistor in place of a transistor identified as a candidate for hardening. The circuit is a latch and the transistor is an SOI CMOS FET. The transistor is also an SOI transistor. The series transistor includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.

Claims

1. A circuit, comprising:

a plurality of hardened, series transistors;

a plurality of non-hardened transistors,

wherein the circuit is a latch,

wherein at least one of the plurality of hardened, series transistors includes transistors that are part of a cross-coupled inverter of the latch; and

a multiplexer circuit, and at least one of the plurality of non-hardened transistors includes a transistor in the latch that is directly connected to a data node, which is directly connected to the multiplexer circuit.

2. The circuit according to claim 1, wherein at least one of the plurality of non-hardened transistors has only a gate terminal connected to a storage node of the latch.

3. The circuit according to claim 2, wherein at least one of the plurality of non-hardened transistors remains ON upon both of the latch holding its state, and a respective storage node at logic state 0, and the latch holding its state, and the respective storage node at logic state 1.

4. The circuit according to claim 2, wherein at least one of the plurality of non-hardened transistors is always driven ON during a default state of the latch.

5. The circuit according to claim 1, wherein the plurality of hardened, series transistors only includes transistors that are part of cross-coupled inverters of the latch.

6. The circuit according to claim 1, wherein a hardened, series transistor is located in all SEU-susceptible transistor nodes of the circuit.

7. The circuit according to claim 1, wherein the circuit includes a master latch and a slave latch, and the at least one non-hardened transistor includes a transistor in the slave latch that is directly connected to a data node, which is directly connected to the master latch.

8. The circuit according to claim 1, wherein a transistor of the plurality of hardened, series transistors is an SOI device.

9. The circuit according to claim 1, wherein one of the plurality of hardened, series transistors includes first and second series-connected transistors having a shared source/drain region whereby a drain of the first series-connected transistor is merged with a source of the second series-connected transistor.