Memory array having local source lines

• US 8,355,272 B2
• Filed: 12/22/2010
• Issued: 01/15/2013
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Everspin Technologies Incorporated
• Inventors: Andre, Thomas
• Primary Examiner(s): Le, Vu
• Application Number:
  US12/975,519
• Publication Number:
  US 20120163061A1
• Time in Patent Office: 755 Days
• Field of Search: 365/148, 365/157, 365/189.15, 365/189.16
• US Class Current: 365/148
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access

Abstract

A memory is provided that simplifies a fabrication process and structure by reducing the number of source lines and bitlines accessible to circuitry outside of the memory array. The memory has first and second row groups comprising a plurality of memory elements each coupled to one each of a plurality of M bit lines; first and second local source lines and first and second word lines, each coupled to each of the plurality of memory elements; and circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in the selected row group coupled to one of the plurality of M bit lines by applying current of magnitude less than N to two or more of the remaining M-1 bit lines.

Claims

1. A memory comprising:

a first plurality of memory elements comprising a first row group, each of the first plurality of memory elements having a first terminal, a second terminal, and a third terminal;

a second plurality of memory elements comprising a second row group, each of the second plurality of memory elements having a fourth terminal, a fifth terminal, and a sixth terminal;

a first plurality of M bit lines, each configured to be coupled to one of the first terminals and one of the fourth terminals;

a first local source line coupled to the second terminals;

a second local source line coupled to the fifth terminals;

a first word line coupled to the third terminals;

a second word line coupled to the sixth terminals; and

circuitry coupled to the first and second word lines and configured to select one of the first and second row groups, and coupled to the first plurality of M bit lines and configured to apply a current of magnitude N through the memory element in the selected row group coupled to one of the first plurality of M bit lines by applying the current of magnitude less than N to two or more of the remaining M-1 bit lines.

2. The memory of claim 1, wherein the current of magnitude N may flow in either direction between the first and second terminals of the first plurality of memory elements, or between the fourth and fifth terminals of the second plurality of memory elements.

3. The memory of claim 1, wherein each of the first and second plurality of memory elements comprise a magnetic tunnel junction.

4. The memory of claim 1, wherein the current of magnitude N changes a state of the memory element in the selected row group, and the current of magnitude less than N does not change the state of the memory elements coupled to the remaining M-1 bit lines.

5. The memory of claim 1, wherein the circuitry providing the current of magnitude N is configured to read the state of the memory element in the selected row group.

6. The memory of claim 1, wherein the circuitry is configured to detect a voltage applied to the local source line of a selected row group through one of the remaining M-1 bit lines.

7. The memory of claim 1, further comprising:

a third plurality of memory elements comprising a third row group and having a seventh terminal, an eighth terminal, and a ninth terminal, the ninth terminal coupled to the first word line;

a second plurality of M bit lines, each configured to be coupled to the seventh terminal; and

a third local source line coupled to the eighth terminal.

8. The memory of claim 7, wherein the third local source line is coupled to the first local source line.

9. A memory comprising:

a first plurality of M memory elements comprising a first row group;

a second plurality of M memory elements comprising a second row group, each of the first plurality of M memory elements and each of the second plurality of M memory elements comprising;

a storage device for storing a state of the memory element, the storage device having a first terminal and a second terminal;

a transistor having a first current electrode coupled to the first terminal of the storage device, a second current electrode, and a control electrode;

a plurality of M bit lines, each configured to be coupled to the second terminal of one storage device in the first plurality of M memory elements and the second terminal of one storage device in the second plurality of M memory elements;

a first local source line coupled to the second current electrode of the transistor in each of the first plurality of M memory elements;

a second local source line coupled to the second current electrode of the transistor in each of the second plurality of M memory elements;

a first word line coupled to the control electrode of each of the first plurality of M memory elements;

a second word line coupled to the control electrode of each of the second plurality of M memory elements;

circuitry coupled to the first and second word lines and configured to select one row group along the plurality of M bit lines, and coupled to the plurality of M bit lines and configured to apply a current of magnitude N through the memory element in a selected row group coupled to one of the plurality of M bit lines by applying the current of magnitude less than N to two or more of the remaining M-1 bit lines.

10. The memory of claim 9, wherein each of the first and second plurality of memory elements comprise a magnetic tunnel junction.

11. The memory of claim 9, wherein the current of magnitude N changes the state of the memory element in the selected row group, and the current of magnitude less than N does not change the state of the memory elements coupled to the remaining M-1 bit lines.

12. The memory of claim 9, wherein the circuitry providing the current of magnitude N is configured to read the state of the memory element in the selected row group.

13. The memory of claim 9, wherein the circuitry is configured to detect the voltage applied to the local source line of a selected row group through one of the remaining M-1 bit lines.

14. The memory of claim 9, further comprising:

a third plurality of M memory elements comprising a third row group, each of the third plurality of M memory elements comprising the storage device and the transistor;

a second plurality of M bit lines, each configured to be coupled to the second terminal of one storage device in the third plurality of M memory elements; and

a third local source line coupled to the second current electrode of the transistor in each of the third plurality of M memory elements;

wherein the first word line is coupled to the control electrode of each of the third plurality of M memory elements.

15. A memory comprising:

a first plurality of M memory elements comprising a first row group;

a second plurality of M memory elements comprising a second row group, each of the first plurality of M memory elements and each of the second plurality of M memory elements comprising;

a storage device for storing a state of the memory element, the storage device having a first terminal and a second terminal;

a transistor having a first current electrode coupled to the first terminal of the storage device, a second current electrode, and a control electrode;

a plurality of M bit lines, each configured to be coupled to the second current electrode of one transistor in the first plurality of M memory elements and the second current electrode of one transistor in the second plurality of M memory elements;

a first local source line coupled to the second terminal of the storage device in each of the first plurality of M memory elements;

a second local source line coupled to the second terminal of the storage device in each of the second plurality of M memory elements;

a first word line coupled to the control electrode of each of the first plurality of M memory elements;

a second word line coupled to the control electrode of each of the second plurality of M memory elements;

circuitry coupled to the first and second word lines and configured to select one row group along the plurality of M bit lines, and coupled to the plurality of M bit lines and configured to apply current of magnitude N through the memory element in a selected row group coupled to one of the plurality of M bit lines by applying a current of magnitude less than N to two or more of the remaining M-1 bit lines.

16. The memory of claim 15, wherein each of the first and second plurality of memory elements comprise a magnetic tunnel junction.

17. The memory of claim 15, wherein the current of magnitude N changes the state of the memory element in the selected row group, and the current of magnitude less than N does not change the state of the memory elements coupled to the remaining M-1 bit lines.

18. The memory of claim 15, wherein the circuitry providing the current of magnitude N is configured to read the state of the memory element in the selected row group.

19. The memory of claim 15, wherein the circuitry is configured to detect a voltage applied to the local source line of a selected row group through one of the remaining M-1 bit lines.

20. The memory of claim 15, further comprising:

a third plurality of M memory elements comprising a third row group, each of the third plurality of M memory elements comprising the storage device and the transistor;

a second plurality of M bit lines, each configured to be coupled to the second terminal of one storage device in the third plurality of M memory elements; and

a third local source line coupled to the second current electrode of the transistor in each of the third plurality of M memory elements;

wherein the first word line is coupled to the control electrode of each of the third plurality of M memory elements.