Circuit for aligning clock to parallel data

• US 8,355,478 B1
• Filed: 05/29/2009
• Issued: 01/15/2013
• Est. Priority Date: 05/29/2009
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Seefeldt, James Douglas, Roper, Weston, Hansen, James
• Primary Examiner(s): Fotakis, Aristocratis
• Application Number:
  US12/475,414
• Time in Patent Office: 1,327 Days
• Field of Search: 375/376, 375/373, 375/344, 375/375, 375/355, 327/156, 327/158, 327/161, 327/163, 370/518, 370/536, 331/12
• US Class Current: 375/355
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop

Abstract

Method and system for aligning a clock signal to parallel data are described. According to one embodiment, a clock shifting circuit shifts an incoming clock signal relative to an incoming data signal, and a data clocking circuit uses the shifted clock signal to reclock the incoming data signal. The clock shifting circuit may comprise a phase locked loop (PLL) coupled with multiple D flip flops (DFFs) connected in series. Divisional combinatorial logic may be disposed between DFFs in the series. Data clocking circuits may comprise one DFF to reclock each incoming data bit, a pair of DFFs to reclock each incoming data bit, or other circuits such as true-complement blocks to serve as local oscillators to mixers. Multiple shifted clock signals may be produced, such as those shifted 60, 90, 120, 180, 240, and 270 degrees relative to the incoming clock signal.

Claims

1. A system for aligning clock and data signals comprising:

a clock shifting circuit, receiving an incoming clock signal and outputting a shifted clock signal, comprising;

a phase locked loop (PLL) with a reference input, a feedback input, and a PLL output, wherein the incoming clock signal connected to the reference input;

a plurality of n D flip flops connected in series, each D flip flop having a D input, a clock input, a Q output, and a Q-bar output, wherein the PLL output is connected to the clock input of every D flip flop, wherein the Q output of a D flip flop is connected to the D input of a subsequent D flip flop in the series, wherein the Q-bar output of a last D flip flop in the series is connected to the D input of a first D flip flop in the series, wherein the Q-bar output of the last D flip flop in the series is buffered and connected to the feedback input, where n is an integer; and

wherein the shifted clock signal is at least one Q output from the series of D flip flops; and

a data clocking circuit, receiving the shifted clock signal and a plurality of incoming data bits and outputting a plurality of reclocked data bits.

2. The system of claim 1, wherein the plurality of n D flip flops connected in series comprises DFF_x, wherein DFF_x is the xth D flip flop in the series, where x is an integer, wherein the Q output of DFF_x transmits the shifted clock signal, and wherein the shifted clock signal has a phase shift of (360/2n)x degrees relative to the incoming clock signal.

3. The system of claim 1, wherein the data clocking circuit comprises:

a true-complement block receiving the shifted clock signal and outputting a true output and a complement output,

wherein the true output carries a clock signal that has a phase shift of (360/2n)x degrees relative to the incoming clock signal, and the complement output carries a clock signal that has a phase shift of (360/2n)x+180 degrees relative to the incoming clock signal, where x is an integer.

4. The system of claim 1, wherein the data clocking circuit comprises:

a plurality of D flip flops, each having a D input, a clock input, and a Q output, wherein each incoming data bit is connected to the D input of one D flip flop, wherein the shifted clock signal is connected to the clock input of all of the plurality of D flip flops, and wherein the Q outputs of the plurality of D flip flops are reclocked data bits.

5. The system of claim 1, wherein the data clocking circuit comprises:

a plurality of D flip flops pairs, each pair comprising two D flip flops, each D flip flop having a D input, a clock input, and a Q output, wherein each incoming data bit is connected to both D inputs of one D flip flop pair, wherein one of the pair of clock inputs is connected to the shifted clock signal and one of the pair of clock inputs is connected to an inverted shifted clock signal, and wherein the pair of Q outputs together constitute a single reclocked data bit.

6. The system of claim 1, wherein the shifted clock signal has a phase shift of 90 degrees relative to the incoming clock signal.

7. The system of claim 1, wherein the buffering on the feedback input of the PLL is matched to a total delay through the plurality of D flip flops.

8. The system of claim 1, wherein n equals 2, wherein the shifted clock signal is the Q output of the first D flip flop, and further comprising:

a first true-complement block having a first input, a first true output, and a first complement output, wherein the shifted clock signal is connected to the first input; and

a second true-complement block having a second input, a second true output, and a second complement output, wherein the Q-bar output of the second D flip flop is connected to the second input, and

wherein the first true output carries a clock signal that has a phase shift of 90 degrees relative to the incoming clock signal, the first complement output carries a clock signal that has a phase shift of 270 degrees relative to the incoming clock signal, the second true output carries a clock signal that is not phase shifted relative to the incoming clock signal, and the second complement output carries a clock signal that is phase shifted 180 degrees relative to the incoming clock signal.

9. The system of claim 8, wherein the data clocking circuit further comprises a four-quadrant mixer that receives all of the incoming data bits, wherein all four of the outputs of the first and second true-complement blocks constitute a local oscillator that drives the four-quadrant mixer, and wherein the four-quadrant mixer is configured to downconvert a modulated signal.

10. A system for aligning clock and data signals comprising:

a clock shifting circuit, receiving an incoming clock signal and generating as output a first shifted clock signal and a second shifted clock signal, comprising;

a phase locked loop (PLL) with a reference input, a feedback input, and a PLL output, wherein the incoming clock signal is connected to the reference input;

a first D flip flop having a first D input, a first clock input, a first Q output, and a first Q-bar output, wherein the PLL output is connected to the first clock input, wherein the first Q output is the first shifted clock signal;

a divisional combinatorial logic block receiving at least one input from the first D flip flop and generating at least one output; and

a second D flip flop having a second D input, a second clock input, a second Q output, and a second Q-bar output, wherein the PLL output is connected to the second clock input, wherein the output of the divisional combinatorial logic block is connected to the second D input, wherein the second Q-bar output is connected to the first D input, wherein the second Q-bar output is buffered and connected to the feedback input, wherein the second Q-bar output is the second shifted clock signal; and

a data clocking circuit, receiving the first and second shifted clock signals and a plurality of incoming data bits and outputting a plurality of reclocked data bits.

11. The system of claim 10, wherein the divisional combinatorial logic block comprises a NOR gate, creating a NOR output from the logic operation of Not-OR (NOR) on the first Q-bar output and the output of an inverter connected to the PLL output.

12. The system of claim 10, wherein the first shifted clock signal has a phase shift of 120 degrees relative to the incoming clock signal and the second shifted clock signal has a phase shift of 240 degrees relative to the incoming clock signal.

13. The system of claim 10, wherein the first shifted clock signal has a phase shift of 120 degrees relative to the reclocked data bits and the second shifted clock signal has a phase shift of 240 degrees relative to the reclocked data bits.

14. The system of claim 10, wherein the data clocking circuit comprises:

a plurality of D flip flops, each having a D input, a clock input, and a Q output, wherein each incoming data bit is connected to the D input of one D flip flop, wherein the first shifted clock signal is connected to at least one of the clock inputs of the plurality of D flip flops, wherein the second shifted clock signal is connected to at least one of the clock inputs of the plurality of D flip flops, and wherein the Q outputs of the plurality of D flip flops are reclocked data bits.

15. The system of claim 10, wherein the data clocking circuit comprises:

a plurality of D flip flops pairs, each pair comprising two D flip flops, each D flip flop having a D input, a clock input, and a Q output, wherein each incoming data bit is connected to both D inputs of one D flip flop pair, wherein one of the pair of clock inputs is connected to one of the first and second shifted clock signals and one of the pair of clock inputs is connected to an inverse of the same shifted clock signal, and wherein the pair of Q outputs together constitute a single reclocked data bit.

16. The system of claim 10, wherein the first shifted clock signal is coupled to a first buffer, wherein the second shifted clock signal is coupled to a second buffer, and wherein the first buffer and the second buffer are matched.

17. A method of aligning clock and data signals, comprising:

receiving at a reference clock input of a phase locked loop (PLL) an incoming clock signal at a first frequency,

generating a modified clock signal at a second frequency using the PLL, wherein the PLL also receives feedback Q signal at a feedback input, wherein the PLL multiplies the incoming clock signal so that the second frequency is greater than the first frequency;

receiving the modified clock signal at a first clock input of a first D flip flop, wherein the first D flip flop also receives the feedback Q signal at a first D input;

generating a shifted clock signal at a third frequency using the first D flip flop, wherein the third frequency is less than the second frequency, and wherein the shifted clock signal is phase-shifted relative to the incoming clock signal;

transmitting the shifted clock signal to a second D input at a second D flip flop;

receiving the modified clock signal at a second clock input of a second D flip flop;

generating the feedback Q signal at a second Q-bar output of the second D flip flop; and

applying the shifted clock signal to logic circuitry to which an incoming data signal is applied.

18. The method of claim 17, wherein the first frequency and the third frequency are the same and wherein the shifted clock signal is phase shifted 90 degrees relative to the incoming clock signal.

19. The method of claim 17, wherein the logic circuitry comprises a plurality of D flip flops.

20. The method of claim 17, wherein transmitting the shifted clock signal to a second D input at a second D flip flop comprises:

receiving the modified clock signal at clock inputs of each of a plurality of D flip flops connected in series;

receiving at a D input of a first D flip flop in the plurality the shifted clock signal;

transmitting a signal from a Q output of each D flip flop in the plurality to a D input of a subsequent D flip flop in the plurality; and

transmitting a last Q signal from a Q output of a last D flip flop in the plurality to the second D input of the second D flip flop.