Parallel encryption/decryption
First Claim
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1. An encryption/decryption device, comprisingan input logic circuit;
- an output logic circuit; and
a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit, each encryption/decryption circuit being capable of processing data at a respective encryption/decryption rate,wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit, andwherein the number of encryption/decryption circuits is equal to or greater than an interface throughput rate divided by the encryption/decryption rate, and the input logic circuit operates to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of encryption/decryption circuits according to a distribution order.
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Abstract
The present disclosure includes methods and devices for parallel encryption/decryption. In one or more embodiments, an encryption/decryption device includes an input logic circuit, an output logic circuit, and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit. For example, each encryption/decryption circuit can be capable of processing data at an encryption/decryption rate, and the number of encryption/decryption circuits can be equal to or greater than an interface throughput rate divided by the encryption/decryption rate.
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Citations
35 Claims
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1. An encryption/decryption device, comprising
an input logic circuit; -
an output logic circuit; and a number of encryption/decryption circuits arranged in parallel between the input logic circuit and the output logic circuit, each encryption/decryption circuit being capable of processing data at a respective encryption/decryption rate, wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit, and wherein the number of encryption/decryption circuits is equal to or greater than an interface throughput rate divided by the encryption/decryption rate, and the input logic circuit operates to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of encryption/decryption circuits according to a distribution order. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A solid state memory system, comprising
at least one memory device; - and
a controller communicatively coupled to the at least one memory device, and having an encryption/decryption device, the encryption/decryption device including; a input multiplexer; an output multiplexer; and a number of encryption/decryption circuits arranged in parallel between the input multiplexer and the output multiplexer, each encryption/decryption circuit being capable of processing data at a respective encryption/decryption rate, wherein the number of encryption/decryption circuits is equal to or greater than an interface throughput rate divided by the encryption/decryption rate, and wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit, wherein the input multiplexer operates to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of encryption/decryption circuits according to a distribution order. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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21. A memory controller, comprising
a host interface configured to be communicatively coupled to a host through a communication interface having a throughput rate; -
a front end direct memory access (DMA) communicatively coupled to the host interface; a number of back end memory channels communicatively coupled to the front end DMA; and an encryption/decryption device communicatively coupled between the host interface and the number of back end memory channels, the encryption/decryption device including a number of encryption/decryption circuits arranged in parallel, each encryption/decryption circuit being capable of processing data at an encryption/decryption rate, wherein the number of parallel encryption/decryption circuits is at least the throughput rate divided by the encryption/decryption rate, and wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit, and wherein the encryption/decryption device is configured to parse an input data stream into a number of groups, and distribute the number of groups to at least some of the number of encryption/decryption circuits according to a distribution order.
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22. A encryption/decryption method, comprising
parsing an input data stream into a number of groups, the input data stream having an interface uppermost throughput rate; - and
distributing the number of groups in a round robin sequence among a number of parallel encryption/decryption circuits operating in an electronic codebook mode, one group being distributed per each selection of a particular encryption/decryption circuit in the round robin sequence; and processing a particular group at a time through one of the number of parallel encryption/decryption circuits at an encryption/decryption rate, wherein the number of parallel encryption/decryption circuits is at least the uppermost throughput rate divided by the encryption/decryption rate, and wherein initialization vectors are combined with a first number of groups parsed from an input data stream to each parallel encryption/decryption circuit, the initialization vectors are incremented for a first parallel encryption/decryption circuit, and the incremented initialization vectors are used as initialization vectors for a second parallel encryption/decryption circuit. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A encryption/decryption method, comprising
parsing an input data stream into a number of groups, the input data stream having an interface uppermost throughput rate; - and
distributing the number of groups in a round robin sequence among a number of parallel encryption/decryption circuits operating in a cipher block chaining mode, a plurality of the groups being distributed per each selection of a particular encryption/decryption circuit in the round robin sequence; processing one group of the plurality of groups at a time through one of the number of parallel encryption/decryption circuits at an encryption/decryption rate combining initialization vectors with a first number of groups to each parallel encryption/decryption circuit; incrementing the initialization vectors for a first parallel encryption/decryption circuit; and using the incremented initialization vectors as initialization vectors for a second parallel encryption/decryption circuit, wherein the number of parallel encryption/decryption circuits is at least the uppermost throughput rate divided by the encryption/decryption rate. - View Dependent Claims (34, 35)
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Specification