Method and system of reducing latencies associated with resource allocation by using multiple arbiters

• US 8,356,128 B2
• Filed: 09/16/2008
• Issued: 01/15/2013
• Est. Priority Date: 09/16/2008
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Mittal, Aditya
• Primary Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US12/211,126
• Publication Number:
  US 20100070667A1
• Time in Patent Office: 1,582 Days
• Field of Search: 710306-315, 710104-119, 710 22- 28, 710240-242
• US Class Current: 710/242
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines

Abstract

A digital processing system employing multiple arbiters, all designed to allocate a resource to a same entity in response to a same condition. In an embodiment, the entities needing the resource may send a request to all the arbiters, and the specific entity to which the resource is allocated, receives indication of the allocation from a closest one of the arbiters. As a result, the latency in receipt of indication of allocation may be reduced. The features are described in the context of a bus as a resource.

Claims

1. A digital processing system comprising:

a plurality of electronic components;

an electronic resource is operable to be used exclusively by one of said plurality of electronic components at a given time; and

a plurality of arbiters, wherein each of said plurality of arbiters is operable to allocate said electronic resource to a same electronic component in response to a same condition.

2. The digital processing system of claim 1, wherein each of said plurality of electronic components is operable to send a request to all of said plurality of arbiters to access said electronic resource.

3. The digital processing system of claim 1, further comprising:

a plurality of response lines, wherein each electronic component of said plurality of electronic components is coupled to a closest arbiter of said plurality of arbiters via an associated response line of said plurality of response lines, and wherein a closest arbiter of said plurality of arbiters is operable to communicate allocation of said electronic resource to an electronic component via said associated response line.

4. The digital processing system of claim 1, further comprising:

a plurality of request lines associated with each electronic component of said plurality of electronic components, wherein said plurality of request lines is operable to communicate access request by an electronic component to said plurality of arbiters.

5. The digital processing system of claim 1, further comprising:

a clock generator operable to generate a clock signal comprising clock cycles, wherein one of said plurality of arbiters is operable to communicate allocation of said electronic resource to an electronic component requesting access to said electronic resource within one clock cycle of said clock signal from said request.

6. The digital processing system of claim 5, wherein a period of said clock signal is less than or equal to 3 nano seconds.

7. The digital processing system of claim 1, wherein said electronic resource is a bus, and wherein said plurality of electronic components comprises a bridge, a processor and a direct memory access (DMA) controller.

8. The digital processing system of claim 7, wherein said processor is a single central processing unit (CPU), and wherein said plurality of arbiters is positioned external to said single CPU.

9. A digital processing system comprising:

a plurality of electronic components;

a first bus operating according to a clock signal comprising a plurality of clock cycles, wherein said first bus is operable to be used exclusively by one of said plurality of electronic components at any given time; and

a plurality of arbiters, wherein each arbiter of said plurality of arbiters is operable to allocate said first bus to a specific electronic component for a subset of said plurality of clock cycles, wherein said allocation is responsive to a plurality of conditions.

10. The digital processing system of claim 9, wherein said specific electronic component is operable to transmit a request to access said first bus to said plurality of arbiters.

11. The digital processing system of claim 9, further comprising:

a central processing unit (CPU) coupled to said first bus, wherein said CPU is one of said plurality of electronic components;

a second bus operating at a lower speed compared to said first bus;

a peripheral interface coupled to said second bus; and

a bridge coupling said first bus to said second bus, wherein said bridge is one electronic component of said plurality of electronic components.

12. The digital processing system of claim 9, wherein said plurality of electronic components comprises a graphics controller coupled to said first bus.

13. The digital processing system of claim 9, wherein a period of said first clock signal is less than or equal to 3 nano seconds.

14. The digital processing system of claim 9, wherein an arbiter that is positioned closest to said specific electronic component in comparison to other arbiters of said plurality of arbiters communicates allocation of said first bus to said specific electronic.

15. A method of allocating a shared electronic resource to a first electronic component, said method comprising:

receiving at each of a plurality of arbiters a request to access said shared electronic resource, wherein said request is initiated by said first electronic component, and wherein said first electronic component is operable to exclusively access said shared electronic resource when said request is granted;

each of said plurality of arbiters independently determining that access to said shared electronic resource is to be granted to said first electronic component; and

communicating exclusive allocation of said shared electronic resource to said first electronic component, wherein said communicating is performed by an arbiter that is positioned closest to said first electronic component in comparison to other arbiters of said plurality of arbiters.

16. The method of claim 15, wherein said shared electronic resource is a bus.

17. The method of claim 15, wherein said first electronic component is operable to receive a message associated with said communicating within one clock period of transmitting said request to access said shared electronic resource.

18. The method as described by claim 15 further comprising:

prior to said determining, receiving at each of said plurality of arbiters a request to access said shared electronic resource from a second electronic component, wherein said second electronic component is operable to exclusively access said shared electronic resource when said request is granted.

19. The method of claim 17, wherein said clock period is less than or equal to 3 nano seconds.

20. The method as described by claim 18, wherein an arbiter that is positioned closest to said second electronic component in comparison to other arbiters of said plurality of arbiters communicates exclusive allocation of said shared electronic resource when request by said second electronic component is granted.