Methods for implementing programmable memory controller for distributed DRAM system-in-package (SiP)
First Claim
1. A memory controller system for providing access from connection ports to one or more memory devices comprising:
- a plurality of controller interface devices, each comprising;
an address device for receiving addresses from one or more of the ports and for providing data to outputs of the controller interface,a data device for receiving data from one or more of the ports and for providing the data to outputs of the controller interface, anda control device for receiving control signals from one or more of the ports and providing control signals to outputs to the controller interface;
a plurality of physical interfaces for receiving the control, the address and the data signals from the outputs of the plurality of controller interface devices and providing the received control and data signals to the memory devices; and
a bank management interface for connecting the plurality of controller interfaces to the plurality of physical interfaces, the bank management interface being programmable to selectively implement one of a plurality of modes comprising a first mode and a second mode, wherein,the first mode aggregates the plurality of controller interface devices into an aggregated controller interface device and wherein the bank management interface is configured to provide the aggregated controller interface device with access to each of the plurality of physical interfaces, andthe second mode segments the plurality of controller interface devices among a plurality of regions and the plurality of physical interfaces among the plurality of regions and wherein the bank management interface is configured to provide controller interface devices with access only to physical interfaces that are within the same region.
1 Assignment
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Accused Products
Abstract
A multi-port memory controller (MPMC) can be parameterized to selectively connect to different memory configurations. In particular, a programmable device that is combined with a DRAM in a die-stacked distributed memory in a single chip is provided with the programmable device forming the MPMC. The programmable device is parameterized to form a memory controller that can either aggregate or segment memory controller components to control different DRAM memory banks either together or separately. The aggregation or segmentation of the memory devices can be configured dynamically during operation of the programmable device.
44 Citations
20 Claims
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1. A memory controller system for providing access from connection ports to one or more memory devices comprising:
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a plurality of controller interface devices, each comprising; an address device for receiving addresses from one or more of the ports and for providing data to outputs of the controller interface, a data device for receiving data from one or more of the ports and for providing the data to outputs of the controller interface, and a control device for receiving control signals from one or more of the ports and providing control signals to outputs to the controller interface; a plurality of physical interfaces for receiving the control, the address and the data signals from the outputs of the plurality of controller interface devices and providing the received control and data signals to the memory devices; and a bank management interface for connecting the plurality of controller interfaces to the plurality of physical interfaces, the bank management interface being programmable to selectively implement one of a plurality of modes comprising a first mode and a second mode, wherein, the first mode aggregates the plurality of controller interface devices into an aggregated controller interface device and wherein the bank management interface is configured to provide the aggregated controller interface device with access to each of the plurality of physical interfaces, and the second mode segments the plurality of controller interface devices among a plurality of regions and the plurality of physical interfaces among the plurality of regions and wherein the bank management interface is configured to provide controller interface devices with access only to physical interfaces that are within the same region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A non-transitory computer readable medium with instructions stored thereon for programming a memory controller to distribute signals from a plurality of ports to distributed memory devices provided on a die, the instructions comprising code to perform steps comprising:
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forming a plurality of controller interface devices for receiving data address and control signals from the ports and providing outputs for transmitting the data, address and control signals; and forming a bank management interface to selectively implement one of a plurality of modes comprising a first mode and a second mode, wherein, the first mode aggregates the plurality of controller interface devices into an aggregated controller interface device and wherein the bank management interface is configured to provide the aggregated controller interface device with access to each of a plurality of physical interfaces, and the second mode segments the plurality of controller interface devices among a plurality of regions and the plurality of physical interfaces among the plurality of regions and wherein the bank management interface is configured to provide controller interface devices with access only to physical interfaces that are within the same region. - View Dependent Claims (13, 14, 15, 16)
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17. A method for controlling access from connection ports to distributed DRAM memories using a device with programmable resources, the method comprising:
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programming logic to provide a plurality of controller interface devices for receiving data, address and control signals from the ports and providing data, address and control signals for distributing to one or more of the DRAM memories; and programming the bank management interface to selectively implement one of a plurality of modes comprising a first mode and a second mode, wherein, the first mode aggregates the plurality of controller interface devices into an aggregated controller interface device and wherein the bank management interface is configured to provide the aggregated controller interface device with access to each of a plurality of physical interfaces, and the second mode segments the plurality of controller interface devices among a plurality of regions and the plurality of physical interfaces among the plurality of regions and wherein the bank management interface is configured to provide controller interface devices with access only to physical interfaces that are within the same region. - View Dependent Claims (18, 19, 20)
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Specification