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Memory controller for non-sequentially prefetching data for a processor of a computer system

  • US 8,356,142 B1
  • Filed: 11/12/2003
  • Issued: 01/15/2013
  • Est. Priority Date: 11/12/2003
  • Status: Active Grant
First Claim
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1. A method for implementing a non-sequential prefetch of data for a processor of a computer system, comprising:

  • storing a plurality of address pairs as leg entries in a table data structure of a memory controller that couples to the processor via a front side bus and couples to a system memory via a system memory bus, the address pairs including a first address and a second address, wherein the first address and the second address are non-sequential as fetched by a processor of a computer system due to a branch instruction execution;

    prioritizing the address pairs in accordance with a frequency of use for each of the address pairs;

    accessing system memory and storing a plurality of cache lines corresponding to the address pairs in a prefetch cache; and

    upon a cache hit during a subsequent access by the processor, decrementing a confidence value upon a hit on the corresponding leg entry; and

    incrementing the confidence value when there is no hit on the corresponding leg entry and a hit on the second address transferring data from the cache lines stored in the prefetch cache to the processor.

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