Vector processor system

• US 8,356,144 B2
• Filed: 05/29/2009
• Issued: 01/15/2013
• Est. Priority Date: 02/10/2005
• Status: Active Grant

• Current Assignee: Chetana N. Keltcher, Korbin S Van Dyke, Nathan Daniel Tuck, Richard Hessel
• Original Assignee: Chetana N. Keltcher, Korbin S Van Dyke, Nathan Daniel Tuck, Richard Hessel
• Inventors: Hessel, Richard, Keltcher, Chetana N., Tuck, Nathan Daniel, Van Dyke, Korbin S.
• Primary Examiner(s): PEUGH, BRIAN R
• Application Number:
  US12/475,393
• Publication Number:
  US 20090300323A1
• Time in Patent Office: 1,327 Days
• Field of Search: None
• US Class Current: 711/154
• CPC Class Codes: G06F 15/8061 Details on data memory access
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A vector processing system provides high performance vector processing using a System-On-a-Chip (SOC) implementation technique. One or more scalar processors (or cores) operate in conjunction with a vector processor, and the processors collectively share access to a plurality of memory interfaces coupled to Dynamic Random Access read/write Memories (DRAMs). In typical embodiments the vector processor operates as a slave to the scalar processors, executing computationally intensive Single Instruction Multiple Data (SIMD) codes in response to commands received from the scalar processors. The vector processor implements a vector processing Instruction Set Architecture (ISA) including machine state, instruction set, exception model, and memory model.

Claims

1. A system comprising:

a plurality of floating point execution units compatible with operation according to a plurality of execution threads;

a plurality of memory channels each enabled to access at least one Dynamic Random Accessible read/write Memory (DRAM) element;

a memory buffer switch unit coupling the floating point execution units to the memory channels;

an instruction control unit enabled to control the floating point execution units according to a stream of vector instructions;

a processor interface compatible with an x86 processor and enabled to receive the stream of vector instructions from the x86 processor;

and wherein the memory buffer switch unit is enabled to consolidate at least two memory requests from the floating point execution units into a single memory access operation directed to one of the memory channels and the at least two memory requests are processed according to a coherency domain implemented by the x86 processor, and wherein respective parts of multiple vector instructions are executed independently by respective ones of the floating point execution units.

2. The system of claim 1, having a Reed-Solomon ECC, enabling ChipKill Functionality with a single DIMM of x4 DRAMs.

3. The system of claim 1, further comprising a page-walking block, and wherein a miss in an Instruction TLB (ITLB) is filled by the page walking block without assistance of the x86 processor.

4. The system of claim 1, wherein the floating point execution units and the processor interface are implemented in a single integrated circuit die.

5. The system of claim 4, wherein the integrated circuit die and the x86 processor are included in a multi-chip module.

6. The system of claim 1, wherein the x86 processor is enabled to control a first one of the execution threads and another x86 processor is enabled to control a second one of the execution threads.

7. The system of claim 1, further comprising a cache tag data structure to track cache state changes of the x86 processor according to the coherency domain.

8. The system of claim 1, wherein the at least two memory requests are unordered via hardware and memory ordering is restored with coherency commands issued by software.

9. The system of claim 1, further comprising a filter to eliminate unnecessary memory probes for reads and writes.

10. The system of claim 1, wherein the floating point execution units are enabled to operate concurrently on parts of a same vector instruction.

11. The system of claim 10, wherein the x86 processor is enabled to control the floating point execution units through a compatible interface.

12. The system of claim 11, wherein the floating point execution units are enabled to share access to coherent memory.

13. A method comprising:

operating a plurality of execution threads on a plurality of floating point execution units;

accessing at least one Dynamic Random Accessible read/write Memory (DRAM) element via a plurality of memory channels;

coupling the floating point execution units to the memory channels via a memory buffer switch unit;

controlling the floating point execution units according to a stream of vector instructions;

receiving the stream of vector instructions from an x86 processor via a processor interface compatible with the x86 processor;

consolidating at least two memory requests from the floating point execution units into a single memory access operation directed to one of the memory channels, and processing the at least two memory requests according to a coherency domain implemented by the x86 processor and

independently executing respective parts of multiple vector instructions by respective ones of the floating point execution units.

14. The method of claim 13, wherein the floating point execution units and the processor interface are implemented in a single integrated circuit die.

15. The method of claim 14, wherein the integrated circuit die and the x86 processor are included in a multi-chip module.

16. The method of claim 13, wherein the at least two memory requests are unordered via hardware and further comprising restoring memory ordering via issuing coherency commands by software.

17. The method of claim 13, further comprising the floating point execution units operating concurrently on parts of a same vector instruction.

18. The method of claim 13, further comprising the floating point execution units sharing access to coherent memory.