Initiative wear leveling for non-volatile memory
First Claim
Patent Images
1. A method comprising:
- counting erase cycles for each of a plurality of memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including;
incrementing a first count of erase cycles for a physical block address of the memory block, andif the memory block is not a spare memory block, incrementing a second count of erase cycles for a logical block address of the memory block;
determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks, wherein wear refers to the usage of the memory blocks of the non-volatile memory; and
if the non-volatile memory has uneven wear of memory blocks, then performing swapping of worn block groups;
wherein determining whether the non-volatile memory has uneven wear of memory blocks includes comparing a slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold.
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Abstract
A method and apparatus for initiative wear leveling for non-volatile memory. An embodiment of a method includes counting erase cycles for each of a set of multiple memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including incrementing a first count for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count for a logical block address of the memory block. The method also includes determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks.
46 Citations
16 Claims
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1. A method comprising:
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counting erase cycles for each of a plurality of memory blocks of a non-volatile memory, the counting of erase cycles for each memory block including; incrementing a first count of erase cycles for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count of erase cycles for a logical block address of the memory block; determining whether the non-volatile memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks, wherein wear refers to the usage of the memory blocks of the non-volatile memory; and if the non-volatile memory has uneven wear of memory blocks, then performing swapping of worn block groups; wherein determining whether the non-volatile memory has uneven wear of memory blocks includes comparing a slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A non-volatile memory device comprising:
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a memory array, the memory array including a plurality of memory blocks, each memory block having a physical block address, and each memory block either having a logical block address or being a spare memory block; and a memory controller coupled with the memory array, the memory controller to control the storage of data in the memory array; wherein each of the plurality of memory blocks includes one or more fields to record a number of erase operations in the usage of each memory block, the one or more fields of a memory block including a first field for a count of erase cycles for a physical block address of the memory block and, if the memory block is not a spare, a second field for a count of erase cycles for a logical block address of the memory block; wherein the memory controller is to determine whether the memory array has uneven wear of memory blocks by comparing a slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold. - View Dependent Claims (8, 9, 10, 11)
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12. A system comprising:
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a bus; a flash memory device coupled with the bus, the non-volatile memory device including a plurality of memory blocks; a dynamic random access memory coupled with the bus; and a processor coupled with the bus, the processor to transfer data between the dynamic random access memory and the flash memory device; wherein the system tracks the number of erase cycles for each of the memory blocks by physical block address and by logical block address and determines whether the flash memory device has uneven wear by comparing a slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold. - View Dependent Claims (13)
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14. A non-transitory computer-readable storage medium having stored thereon data representing sequences of instructions that, when executed by a processor, cause the processor to perform operations comprising:
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counting erase cycles for each of a plurality of memory blocks of a flash memory, the counting of erase cycles for a memory block including; incrementing a first count of erase cycles for a physical block address of the memory block, and if the memory block is not a spare memory block, incrementing a second count of erase cycles for a logical block address of the memory block; determining whether the flash memory has uneven wear of memory blocks based at least in part on the counting of the erase cycles of the plurality of memory blocks, wherein wear refers to the usage of the memory blocks of the non-volatile memory; and if the non-volatile memory has uneven wear of memory blocks, then performing swapping of worn block groups; wherein determining whether the non-volatile memory has uneven wear of memory blocks includes comparing a slope of a regression line for the number of erase cycles for each of the memory blocks by physical block address and by logical block address with a slope threshold. - View Dependent Claims (15, 16)
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Specification