Adaptive processor for performing an operation with simple and complex units each comprising configurably interconnected heterogeneous elements

• US 8,356,161 B2
• Filed: 10/15/2008
• Issued: 01/15/2013
• Est. Priority Date: 03/22/2001
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: QST Holdings LLC
• Inventors: Master, Paul L., Hogenauer, Eugene, Scheuermann, Walter James
• Primary Examiner(s): KIM, KENNETH S
• Application Number:
  US12/251,946
• Publication Number:
  US 20090037693A1
• Time in Patent Office: 1,553 Days
• Field of Search: None
• US Class Current: 712/15
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Claims

1. An integrated circuit for performing an operation having at least a simple computational function and a complex processing function, the circuit for performing an operation having at least a simple computational function and a complex processing function, the circuit comprising:

a configurable simple computational unit including a plurality of heterogeneous computational elements coupled to each other via a first interconnection network to configure interconnections between selected ones of the computational elements in response to configuration information to perform the simple computational function of the operation, wherein the configured interconnections remain fixed during the performance of the simple computational function;

a configurable complex processing unit including a second plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure the interconnections between selected ones of the second plurality of computational elements in response to the configuration information to perform the complex processing function of the operation, wherein the configured interconnections remain fixed during the performance of the complex processing function; and

a third interconnection network coupled to the configurable simple computational unit and the configurable complex processing unit, the third interconnection network sending the configuration information to the simple computational unit and the complex processing unit.

2. The integrated circuit of claim 1, wherein the simple computational function is a logic function and the complex processing function is a digital signal processing function.

3. The integrated circuit of claim 1, wherein the simple computational function includes bit level manipulation and the complex processing function includes word level manipulation.

4. The integrated circuit of claim 1, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

5. The integrated circuit of claim 1, wherein the simple computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

6. The integrated circuit of claim 1, wherein the computational units are organized in a computing matrix, and the computing matrix is coupled to a matrix interconnection network.

7. The integrated circuit of claim 6, wherein the matrix interconnection network is coupled to a plurality of computing matrices, each computing matrix having a plurality of computational units.

8. The integrated circuit of claim 1, wherein the first plurality of computational elements are organized as a simple computational architecture and the second plurality of computational elements are organized as a complex processing architecture.

9. The integrated circuit of claim 6, wherein a first configured function of the computational matrix is as a controller including a controller function.

10. The integrated circuit of claim 9, wherein the controller function includes sending configuration information via the matrix interconnection network to configure one of the plurality of configurable computing matrices.

11. The integrated circuit of claim 9, wherein the controller is a RISC controller.

12. The integrated circuit of claim 1, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

13. The integrated circuit of claim 6, wherein the matrix interconnection network transmits configuration information to the computing matrix to configure the computing matrix to perform the function.

14. The integrated circuit of claim 1, wherein the simple computational function includes one of a group of addition, linear operation, memory, and bit level manipulation.

15. The integrated circuit of claim 1, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

16. The integrated circuit of claim 1, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements and the second interconnection network includes multiplexers coupled to the second plurality of heterogeneous computational elements.

17. The integrated circuit of claim 16, wherein the configuration information includes control signals to control the multiplexers.

18. The integrated circuit of claim 1, wherein the first interconnection network provides second configuration information to reconfigure the configurable simple computational unit to perform a second computational function.

19. The integrated circuit of claim 1, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

20. The integrated circuit of claim 1, wherein the complex processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

21. The integrated circuit of claim 1, wherein one type of the second plurality of heterogeneous computational elements are bypassed via the interconnections between the second plurality of computational elements to perform the complex processing function.

22. An integrated circuit for performing an operation having at least a simple bit level computational function and a complex word level processing function, the circuit comprising:

a configurable simple computational logic unit including a first computational architecture formed from a first plurality of heterogeneous computational elements coupled to each other via a first computational interconnection network to configure interconnections between selected ones of the first plurality of heterogeneous computational elements in response to configuration information to perform the simple bit level computational function of the operation, wherein the configured interconnections remain fixed during the performance of the simple bit level computational function; and

a configurable complex processing unit including a second computational architecture formed from a second plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure interconnections between selected ones of the second plurality of computational elements in response to the configuration information to perform the complex word level processing function of the operation, wherein the configured interconnections remain fixed during the performance of the complex word level processing function, wherein the complex word level processing function is performed simultaneously with the simple bit level computational function.

23. The integrated circuit of claim 22, wherein the simple computational function is a logic function and the complex processing function is a digital signal processing function.

24. The integrated circuit of claim 22, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

25. The integrated circuit of claim 22, wherein the simple computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

26. The integrated circuit of claim 22, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

27. The integrated circuit of claim 22, wherein the simple computational function includes one of a group of addition, linear operation, memory, memory management, and bit level manipulation.

28. The integrated circuit of claim 22, further comprising a third interconnection network coupled to the configurable simple computational unit and the configurable complex processing unit, the third interconnection network sending the configuration information to the computational units.

29. The integrated circuit of claim 28, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

30. The integrated circuit of claim 22, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements and the second interconnection network includes multiplexers coupled to the second plurality of heterogeneous computational elements.

31. The integrated circuit of claim 30, wherein the configuration information includes control signals to control the multiplexers.

32. The integrated circuit of claim 22, wherein the first interconnection network provides second configuration information to reconfigure the first configurable simple computational unit to perform a second simple computational function.

33. The integrated circuit of claim 22, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

34. The integrated circuit of claim 22, wherein the complex processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

35. The integrated circuit of claim 22, wherein one type of the second plurality of heterogeneous computational elements are bypassed via the interconnections between the second plurality of computational elements to perform the complex processing function.

36. An integrated circuit for performing an operation having at least a simple computational function and a complex processing function, the circuit comprising:

a first configurable simple computational unit including a first plurality of heterogeneous computational elements forming a first computational architecture, the first plurality of heterogeneous computational elements each coupled to each other via a first interconnection network to configure interconnections between the computational elements in response to configuration information to perform the simple computational function of the operation, wherein the configured interconnections remain fixed during the performance of the simple computational function; and

a second configurable complex processing unit including a second plurality of heterogeneous computational elements forming a second complex processing architecture, the second plurality of heterogeneous computational elements coupled to each other via a second interconnection network to configure interconnections between the computational elements in response to the configuration information to perform the complex processing function of the operation, wherein the configured interconnections remain fixed during the performance of the complex processing function, the second interconnection network reconfiguring the second configurable complex processing unit to perform another complex processing function by changing some of the interconnections between the heterogeneous computational elements in accordance to other configuration information.

37. The integrated circuit of claim 36, wherein the simple computational function is a logic function and the complex processing function is a digital signal processing function.

38. The integrated circuit of claim 36, wherein the simple computational function includes bit level manipulation and the complex processing function relates to word level functions.

39. The integrated circuit of claim 36, wherein the first plurality of heterogeneous computational elements includes a function generator and an adder, a register and an adder, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the second plurality of heterogeneous computational elements includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

40. The integrated circuit of claim 36, wherein the simple computational function includes a function generator and an adder, an adder and a register, a function generator and a register, or a function generator and an adder and a register, the function generator having data inputs and a control input to selection a specific function;

and

wherein the complex processing function includes a multiplier and an adder, a multiplier and a register, or a multiplier and an adder and a register.

41. The integrated circuit of claim 36, wherein the first interconnection network operates as a Boolean interconnection network and a data interconnection network, the first interconnection network further allowing the transmission of data and configuration information.

42. The integrated circuit of claim 36, wherein the simple computational function includes one of a group of addition, linear operation, memory, memory management, and bit level manipulation.

43. The integrated circuit of claim 36, further comprising a third interconnection network coupled to the configurable simple computational logic unit and the configurable complex processing unit, the interconnection network sending the configuration information to the computational units.

44. The integrated circuit of claim 43, wherein the first interconnection network has denser interconnections than the interconnections of the third interconnection network.

45. The integrated circuit of claim 38, wherein the first interconnection network includes multiplexers coupled to the first plurality of heterogeneous computational elements and the second interconnection network includes multiplexers coupled to the second plurality of heterogeneous computational elements.

46. The integrated circuit of claim 45, wherein the configuration information includes control signals to control the multiplexers.

47. The integrated circuit of claim 36, wherein the first interconnection network provides second configuration information to reconfigure the configurable simple computational unit to perform a second simple computational function.

48. The integrated circuit of claim 36, wherein the second plurality of heterogeneous computational elements each perform a function from the group of multiplication, addition, subtraction, accumulation, summation, byte passing, and dynamic shift.

49. The integrated circuit of claim 36, wherein the complex processing function is one of fixed point arithmetic functions, floating point arithmetic functions, filtering functions, and transformation functions.

50. The integrated circuit of claim 36, wherein one type of the second plurality of heterogeneous computational elements are bypassed via the interconnections between the second plurality of computational elements to perform the complex processing function.