Method and apparatus for estimating overshoot power after estimating power of executing events

• US 8,356,194 B2
• Filed: 01/28/2010
• Issued: 01/15/2013
• Est. Priority Date: 01/28/2010
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Carlson, David A., Kessler, Richard E., Haider, Amer
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Application Number:
  US12/695,648
• Publication Number:
  US 20110185203A1
• Time in Patent Office: 1,083 Days
• Field of Search: 713/300, 713/320, 713/340, 718/100
• US Class Current: 713/320
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 11/3058 Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations thermal management in cooling arrangements of a computing system G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y10S 323/907 Temperature compensation of semiconductor

Abstract

Embodiments of the present invention relate to limiting maximum power dissipation occurred in a processor. Therefore, when an application that requires excessive amounts of power is being executed, the execution of the application may be prevented to reduce dissipated or consumed power. Example embodiments may stall the issue or execution of instructions by the processor, allowing software or hardware to reduce the power of an application by imposing a decrease in the performance of the application.

Claims

1. A method for controlling power in a computer chip, the method comprising:

during a cycle of power control, accumulating power information relating to power consumed during issuing instructions;

comparing accumulated power information against a predetermined threshold;

preventing further instructions from being issued to reduce power consumption in the computer chip, in an event the accumulated power information exceeds the predetermined threshold;

determining power consumed after preventing further instructions from being issued;

adding the power consumed after preventing further instructions from being issued to accumulated power information of a subsequent cycle of power control to obtain a total power value; and

preventing further instructions from being issued in the subsequent cycle of power control in an event the total power value exceeds the predetermined threshold.

2. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions over a predetermined time interval.

3. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions as a function of estimating power associated with each issued instruction.

4. The method of claim 3 further including estimating the power associated with each issued instruction as a function of employing a database of power values associated with known instructions.

5. The method of claim 3 further including estimating the power associated with each issued instruction as a function of determining a number of clock cycles elapsed in processing of the instruction.

6. The method of claim 1 further including accumulating the power information relating to power consumed during issuing instructions over one or more instruction cycles.

7. The method of claim 6 further including preventing further instructions from being issued until one or more instruction cycles have elapsed.

8. The method of claim 6 further including preventing further instructions from being issued until a current throttle period is completed.

9. The method of claim 6 further including preventing further instructions from being issued until a predetermined number of instruction cycles have elapsed.

10. The method of claim 1 further including preventing further instructions from being issued until a predetermined time interval has elapsed.

11. The method of claim 1 further including determining the predetermined threshold as a function of a maximum power allowed in the computer chip.

12. The method of 1 further including determining the predetermined threshold as a function of one or more chip fuses.

13. A processor comprising:

a power accumulator unit configured to accumulate power information relating to power consumed during issuing instructions during a cycle of power control;

a comparison unit configured to compare accumulated power information against a predetermined threshold during the cycle of power control;

a controller unit configured to prevent further instructions from being issued to reduce power consumption, in an event the accumulated power information exceeds the predetermined threshold during the cycle of power control;

an overshoot power estimator configured to estimate power consumed after preventing further instructions from being issued, the consumed power being added to accumulated power information of a subsequent cycle of power control to obtain a total power value; and

the controller unit further configured to prevent further instructions from being issued in the subsequent cycle of power control in an event the total power value exceeds the predetermined threshold during the subsequent cycle of power control.

14. The processor of claim 13 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions over a predetermined time interval.

15. The processor of claim 13 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions as a function of estimating power associated with each issued instruction.

16. The processor of claim 15 further including a power estimator unit configured to estimate the power associated with each issued instruction as a function of employing a database of power values associated with known instructions.

17. The processor of claim 13 further including a power estimator unit configured to estimate the power associated with each issued instruction as a function of determining a number of clock cycles elapsed in processing of the instruction.

18. The processor of claim 13 wherein the power accumulator unit is configured to accumulate the power information relating to power consumed during issuing instructions over one or more instruction cycles.

19. The processor of claim 18 wherein the controller unit is configured to prevent further instructions from being issued until one or more instruction cycles have elapsed.

20. The processor of claim 18 wherein the controller unit is configured to prevent further instructions from being issued until a current throttle period is completed.

21. The processor of claim 18 wherein the controller unit is configured to prevent further instructions from being issued until a predetermined number of instruction cycles have elapsed.

22. The processor of claim 13 wherein the controller unit is configured to prevent further instructions from being issued until a predetermined time interval has elapsed.

23. The processor of claim 13 further wherein the comparison unit is configured to determine the predetermined threshold as a function of a maximum power allowed in the computer chip.

24. The processor of claim 13 further wherein the comparison unit is configured to determine the predetermined threshold as a function of one or more chip fuses.

25. A method for controlling power in a processor, the method comprising:

during a cycle of power control, estimating a first power consumption estimate of power consumed by the processor during processing of one or more events;

preventing further processing in the processor as a function of the first power consumption estimate to reduce power consumption;

estimating power consumed after preventing further processing to determine an overshoot power value; and

in a subsequent cycle of power control, estimating a second power consumption estimate of power consumed by the processor during processing of one or more events and preventing further processing of one or more events in the processor as a function of the second power consumption estimate and the overshoot power value.

26. The method of claim 25 further including estimating power consumed by the processor as a function of a current flowing into the processor.

27. The method of claim 25 further including estimating power consumed by the processor as a function of a switched capacitance created at the processor by each of the one or more events.

28. The method of claim 25 further including accumulating the power estimates over at least one of a predetermined interval of time or a predetermined number of event cycles.

29. The method of claim 28 further including preventing further processing in the processor if accumulated power exceeds a predetermined threshold.

30. The method of claim 28 wherein the one or more events include at least one of an instruction issued by the processor over an event cycle, a conditional clock enabled over the event cycle, and a cache accessed over the event cycle.

31. The method of claim 25 further including preventing further processing as a function of issuing a throttle signal to a queue or issue pipeline of the processor.

32. A processor comprising:

a power estimator configured to estimate a first power consumption estimate of power consumed by the processor during processing of one or more events during a cycle of power control and a second power consumption estimate of power consumed by the processor during processing of one or more events during a subsequent cycle of power control;

a power controller configured to prevent further processing in the processor as a function of the first power consumption estimate to reduce power consumption; and

an overshoot power estimator configured to estimate power consumed after preventing further processing to determine an overshoot power value, wherein the power controller is configured to prevent further processing of one or more events in the processor in the subsequent cycle of power control as a function of the second power consumption estimate and the overshoot power value.

33. The processor of claim 32 wherein the power estimator is configured to estimate the power consumed by the processor as a function of a current flowing into the processor.

34. The processor of claim 32 wherein the power estimator is configured to estimate the power consumed by the processor as a function of a switched capacitance created at the processor by each of the one or more events.

35. The processor of claim 32 further including a power accumulator that accumulates the power estimates over at least one of a predetermined interval of time or a predetermined number of event cycles.

36. The processor of claim 35 wherein the power controller is configured to prevent further processing in the processor if accumulated power exceeds a predetermined threshold.

37. The processor of claim 35 wherein the one or more events include at least one of an instruction issued by the processor over an event cycle, a conditional clock enabled over the event cycle, and a cache accessed over the event cycle.

38. The processor of claim 35 wherein the power controller is configured to prevent further processing as a function of issuing a throttle signal to a queue or issue pipeline of the processor.

39. A method for controlling power consumption, the method comprising:

during a cycle of power control, accumulating first power information relating to power consumed in a unit during execution of one or more tasks and during a subsequent cycle of power control, accumulating second power information relating to power consumed in a unit during execution of one or more tasks;

controlling power consumption in the unit by preventing further execution of the one or more tasks executing during the cycle of power control in an event the accumulated first power information exceeds a predetermined threshold;

estimating overshoot power information relating to power consumed after the preventing of further execution of the one or more tasks; and

preventing further execution of one or more tasks in the subsequent cycle of power control if a combination of the overshoot power information and the second power information exceeds the predetermined threshold.

40. The method of claim 39 further including accumulating the power information as a function of estimating power consumed during execution of each task.

41. The method of claim 40 further including estimating the power consumed as a function of a database of known power values associated with each task.

42. The method of claim 39 further including accumulating the power information in the unit over at least one of a predetermined interval of time or a predetermined number of tasks.

43. The method of claim 39 further including preventing further execution of the one or more tasks as a function of issuing a throttle signal to an execution pipeline of the unit.

44. An apparatus for controlling power consumption, the apparatus comprising:

a power accumulator to accumulate first power information relating to power consumed in a unit during execution of one or more tasks during a cycle of power control and second power information relating to power consumed in a unit during execution of one or more tasks in a subsequent cycle of power control; and

a power controller to control power consumption in the unit by preventing further execution of the one or more tasks executing during the cycle of power control in an event the accumulated first power information exceeds a predetermined threshold, wherein the power controller is arranged to;

estimate overshoot power information relating to power consumed after the preventing of further execution of the one or more tasks; and

in the subsequent cycle of power control, prevent further execution of one or more tasks if a combination of the overshoot power information and the second power information exceeds the predetermined threshold.

45. The apparatus of claim 44 wherein the power accumulator is arranged to accumulate the power information as a function of estimating power consumed during execution of each task.

46. The apparatus of claim 45 wherein the power accumulator includes a power estimator arranged to estimate the power consumed as a function of a database of known power values associated with each task.

47. The apparatus of claim 44 wherein the power accumulator is arranged to accumulate the power information in the unit over at least one of a predetermined interval of time or a predetermined number of tasks.

48. The apparatus of claim 44 wherein the power controller is arranged to prevent further execution of the one or more tasks as a function of issuing a throttle signal to an execution pipeline of the unit.