Enabling a high-level modeling system

• US 8,356,266 B1
• Filed: 04/09/2010
• Issued: 01/15/2013
• Est. Priority Date: 04/09/2010
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Ou, Jingzhao, Chan, Chi Bun, Stroomer, Jeffrey D.
• Primary Examiner(s): DOAN, NGHIA M
• Application Number:
  US12/757,945
• Time in Patent Office: 1,012 Days
• Field of Search: 716116-119, 716/126, 716129-130, 716/139, 716/104, 716121-122
• US Class Current: 716/122
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An embodiment of a method for enabling a high level modeling system for implementing a circuit design in an integrated circuit device includes: receiving a high-level characterization of the circuit design; receiving a portable location constraint associated with elements of the circuit design; and generating, by a computer, a low-level characterization of the circuit design based upon the high-level characterization and the portable location constraint.

Claims

1. A method of enabling a high-level modeling system for implementing a circuit design in an integrated circuit device, the method comprising:

receiving a hardware description language characterization of the circuit design;

identifying elements of the circuit design which are independent of the integrated circuit device;

receiving a portable location constraint associated with elements of the circuit design, wherein the portable location constraint is independent of the integrated circuit device, and identifies an alignment of elements of a group of a common element with respect to one another; and

generating, by a computer during a place and route operation, a low-level characterization of the circuit design based upon the hardware description language characterization and the portable location constraint, wherein the low-level characterization is provided in terms of circuit elements of the integrated circuit device in which the circuit design is implemented.

2. The method of claim 1 wherein receiving a portable location constraint comprises receiving a size factor property.

3. The method of claim 1 wherein receiving a portable location constraint comprises receiving a ratio property.

4. The method of claim 1 wherein receiving a portable location constraint comprises receiving an orientation of elements.

5. The method of claim 4 wherein receiving an orientation of elements comprises receiving a flow of elements.

6. The method of claim 4 wherein receiving an orientation of elements comprises receiving a grouping of elements.

7. The method of claim 1 wherein receiving a portable location constraint further comprises enabling the selection of the portable location constraint based upon a characteristic of the circuit design.

8. A method of enabling a high-level modeling system to implement a circuit design in an integrated circuit device, the method comprising:

identifying elements of a circuit design which are independent of the integrated circuit device;

receiving a hardware description language characterization of the circuit design;

receiving a portable location constraint comprising size information for circuit elements used to implement the circuit design, wherein the portable location constraint is independent of the integrated circuit device, and identifies an alignment of elements of a group of a common element with respect to one another; and

generating, by a computer during a place and route operation, a low level characterization of the circuit design based upon the hardware description language characterization and the size information for the circuit elements, wherein the low-level characterization is provided in terms of circuit elements of the integrated circuit device in which the circuit design is implemented.

9. The method of claim 8 further comprising receiving an orientation of the circuit elements.

10. The method of claim 8 wherein receiving size information for circuit elements comprises receiving a percentage of a circuit block implementing a portion of the circuit design.

11. The method of claim 8 wherein receiving size information for circuit elements comprises receiving relative dimensions of a portion of the circuit design.

12. The method of claim 8 further comprising receiving circuit requirements for a first element of the circuit elements and determining circuit requirements for a second element of the circuit elements based upon the circuit requirements for the first element.

13. The method of claim 8 further comprising implementing the circuit in a device having programmable resources.

14. A non-transitory computer-readable storage medium comprising computer-executable code for enabling a high-level modeling system to implement a circuit design in an integrated circuit device, the computer-executable code comprising:

code for identifying elements of a circuit design which are independent of the integrated circuit device;

code for receiving a hardware description language characterization of the circuit design;

code for receiving a portable location constraint associated with elements of the circuit design, wherein the portable location constraint is independent of the integrated circuit device, and identifies an alignment of elements of a group of a common element with respect to one another; and

code for generating a low-level characterization of the circuit design based upon the hardware description language characterization and the portable location constraint, wherein the low-level characterization is provided in terms of circuit elements of the integrated circuit device in which the circuit design is implemented.

15. The non-transitory computer-readable storage medium of claim 14 wherein the code for receiving a portable location constraint comprises code for receiving a size factor property.

16. The non-transitory computer-readable storage medium of claim 14 wherein the code for receiving a portable location constraint comprises-code for receiving a ratio property.

17. The non-transitory computer-readable storage medium of claim 14 wherein the code for receiving a portable location constraint comprises code for receiving an orientation of elements.

18. The non-transitory computer-readable storage medium of claim 17 wherein the code for receiving an orientation of elements comprises code for receiving a flow of elements.

19. The non-transitory computer-readable storage medium of claim 17 wherein the code for receiving an orientation of elements comprises code for receiving a grouping of elements.

20. The non-transitory computer-readable storage medium of claim 14 further comprising code for enabling the selection of the portable location constraint based upon a characteristic of the circuit design.