Reducing far-end crosstalk in electrical connectors

• US 8,357,013 B2
• Filed: 11/05/2009
• Issued: 01/22/2013
• Est. Priority Date: 01/22/2009
• Status: Active Grant

• Current Assignee: Hirose Electric Company Limited
• Original Assignee: Hirose Electric Company Limited
• Inventors: Arai, Tatsuya, Huang, Ching-Chao, Luk, Clement Kam Lam, Buan, Jeremy, Matsuo, Tsutomu, Takada, Toshiyuki, Nagata, Masakazu
• Primary Examiner(s): Luebke, Renee
• Assistant Examiner(s): TSUKERMAN, LARISA Z
• Application Number:
  US12/613,501
• Publication Number:
  US 20100184307A1
• Time in Patent Office: 1,174 Days
• Field of Search: 439/941, 439/676, 379/417
• US Class Current: 439/676
• CPC Class Codes: H04M 1/76 Compensating for differences in line impedance
• CPC Class Codes: H05K 1/0245 Lay-out of balanced signal pairs, e.g. differential lines or twisted lines
• CPC Class Codes: H05K 2201/09245 Crossing layout alternating conductors H05K2201/097
• CPC Class Codes: H05K 2201/10689 Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]

Abstract

The present invention involves connectors for reducing Far-End Crosstalk (FEXT) through the use of novel polarity swapping to negate the cumulative effect of FEXT. Skew adjustment is used to improve the FEXT cancellation from polarity swapping. The polarity reversal location or locations among FEXT sources are optimized to achieve maximum FEXT cancellation. The novelty polarity swapping technique can be applied to a wide variety of connectors, such as mezzanine connectors, backplane connectors, and any other connectors that can benefit from FEXT reduction.

Claims

1. A three piece connector reducing Far End Crosstalk (FEXT), comprising:

a first receptacle on a transmission end;

a second receptacle on a receiving end;

an interposer detachably connected to the first receptacle and to the second receptacle; and

multiple differential pairs connected to the first receptacle and second receptacle;

each differential pair comprising a positive signal line and a negative signal line wherein the positive signal line and the negative signal line of each of the multiple differential pairs are disposed at relative physical locations to each other;

wherein polarity reversal is achieved by intersecting the positive signal line and the negative signal line of each differential pair undergoing polarity reversal only once within the interposer;

wherein the interposer further comprises a wafer, the multiple differential pairs being disposed on the wafer, and wherein the polarity reversal occurs on the wafer;

wherein multiple first ones of the multiple differential pairs undergo polarity reversal and multiple second ones of the multiple differential pairs do not undergo the polarity reversal,

wherein each of the multiple first ones of the multiple differential pairs is placed adjacent to at least one of the multiple second ones of the multiple differential pairs not undergoing polarity reversal, such that every other one of the multiple differential pairs undergoes polarity reversal.

2. The connector of claim 1, wherein the multiple differential pairs are arranged in a staggered array configuration with respect to each wafer in the interposer.

3. The connector of claim 1, wherein delay is adjusted in at least one differential pair such that skew is reduced.

4. The connector of claim 1, wherein the polarity reversal is achieved at at least one predetermined point optimized to achieve maximum FEXT cancellation.

5. The connector according to claim 1, wherein the positive signal line and the negative signal line of each of said multiple differential pairs do not intersect any positive signal lines and negative signal lines of other ones of the multiple differential pairs.

6. The connector of claim 1, wherein the positive signal line and the negative signal line of each said differential pair undergoing polarity reversal are oriented so that said positive signal line and said negative signal line do not intersect any positive signal lines and negative signal lines of other ones of the multiple differential pairs.

7. The connector according to claim 1, wherein the first receptacle and the second receptacle are substantially equal FEXT sources and wherein the intersecting of physical locations occurs substantially at a middle portion of said wafer.

8. The connector of claim 1, wherein the first receptacle and the second receptacle each comprise pin assignments for connecting to a printed circuit board.

9. The connector of claim 1, wherein the center one of the multiple differential pairs undergoes polarity reversal, and wherein the multiple differential pairs undergoing polarity reversal and the multiple differential pairs not undergoing polarity reversal are alternately positioned with respect to the center one of the multiple differential pairs.

10. The connector of claim 1, wherein the center one of the multiple differential pairs does not undergo polarity reversal, and wherein the multiple differential pairs undergoing polarity reversal and the multiple differential pairs not undergoing polarity reversal are alternately positioned with respect to the center one of the multiple differential pairs.

11. The connector of claim 1, wherein the positive signal line and the negative signal line are positioned on different planes with respect to a z-axis at the intersection.

12. A three piece connector reducing Far End Crosstalk (FEXT), comprising:

a first receptacle on a transmission end;

a second receptacle on a receiving end;

an interposer detachably connected to the first receptacle and to the second receptacle;

at least one single ended signal line; and

multiple differential pairs connected to the first receptacle and the second receptacle;

each differential pair comprising a positive signal line and a negative signal line;

wherein the positive signal line and the negative signal line of each of the multiple differential pairs are disposed at relative physical locations to each other;

wherein the interposer further comprises a wafer, the multiple differential pairs being disposed on the wafer, and wherein the polarity reversal occurs on the wafer;

wherein polarity reversal is achieved by intersecting the positive signal line and the negative signal line of each differential pair undergoing polarity reversal only once within the interposer;

wherein multiple first ones of the multiple differential pairs undergo polarity reversal and multiple second ones of the multiple differential pairs do not undergo the polarity reversal,

wherein each of the multiple first ones of the multiple differential pairs is placed adjacent to at least one of the multiple second ones of the multiple differential pairs not undergoing polarity reversal, such that every other one of the multiple differential pairs undergoes polarity reversal.

13. The connector of claim 12, wherein delay is adjusted in one of the at least one differential pair or in the at least one single-ended signal line such that skew is reduced.

14. The connector of claim 12, wherein the polarity reversal is achieved at at least one predetermined point optimized to achieve maximum FEXT cancellation.

15. The connector according to claim 12, wherein the positive signal line and the negative signal line of each of said multiple differential pairs do not intersect any positive signal lines and negative signal lines of other ones of the multiple differential pairs.

16. The connector of claim 12, wherein the positive signal line and the negative signal line of each said differential pair undergoing polarity reversal are oriented so that said positive signal line and said negative signal line do not intersect any positive signal lines and negative signal lines of other ones of the multiple differential pairs.

17. The connector according to claim 12, wherein the first receptacle and the second receptacle are substantially equal FEXT sources and wherein the intersecting of physical locations occurs substantially at a middle portion of said wafer.

18. The connector of claim 12, wherein the positive signal line and the negative signal line are positioned on different planes with respect to a z-axis at the intersection.