Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics

• US 8,357,610 B2
• Filed: 01/16/2009
• Issued: 01/22/2013
• Est. Priority Date: 03/31/2008
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Feustel, Frank, Werner, Thomas, Grillberger, Michael, Frohberg, Kai
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US12/355,112
• Publication Number:
  US 20090243116A1
• Time in Patent Office: 1,467 Days
• Field of Search: 438/618, 438/627, 438/653, 438/E21.579, 438637-643
• US Class Current: 438/637
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2221/1063 Sacrificial or temporary thin dielectric films in openings in a dielectric
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

By forming a protection layer prior to the application of the planarization layer during a dual damascene strategy for first patterning vias and then trenches, enhanced etch fidelity may be accomplished. In other aspects disclosed herein, via openings and trenches may be patterned in separate steps, which may be accomplished by different etch behaviors of respective dielectric materials and/or the provision of an appropriate etch stop layer, while filling the via opening and the trench with a barrier material and a highly conductive metal may be achieved in a common fill sequence. Hence, the via opening may be formed on the basis of a reduced aspect ratio, while nevertheless providing a highly efficient overall process sequence.

Claims

1. A method, comprising:

forming a via opening in a low-k dielectric layer formed above a substrate of a semiconductor device;

forming a protection layer on exposed surface portions of said low-k dielectric layer, said protection layer covering an upper surface of said low-k dielectric layer and sidewall surfaces of said via opening;

forming a planarization material on said protection layer, said planarization material filling said via opening and covering said upper surface of said low-k dielectric layer;

forming a trench opening in said planarization material formed above said upper surface of said low-k dielectric layer while removing a first portion of said planarization material from said via opening, wherein said trench opening is positioned above said via opening; and

forming a trench in said low-k dielectric layer on the basis of said trench opening in said planarization material.

2. The method of claim 1, wherein forming said protection layer comprises forming a dielectric material on said exposed surface portions.

3. The method of claim 1, wherein forming said protection layer comprises forming a conductive material on said exposed surface portions and removing a portion of said conductive material outside said via opening after forming said trench.

4. The method of claim 1, further comprising removing said protection layer in said via opening after forming said trench.

5. The method of claim 1, further comprising filling said via opening and said trench with a metal in a common fill process.

6. The method of claim 5, further comprising forming a conductive barrier layer at least in said trench prior to filling said via opening and said trench with a metal.

7. The method of claim 1, further comprising, after forming said trench in said low-k dielectric layer, removing remaining portions of said planarization material and deepening said via opening so as to extend to a metal region.

8. The method of claim 1, wherein said via opening is formed so as to extend to a metal region located below said low-k dielectric layer.

9. The method of claim 8, further comprising forming a conductive barrier layer on a portion of said metal region exposed by said via opening.

10. The method of claim 1, further comprising forming a conductive barrier layer inside of said trench and said via opening prior to filling said trench and said via opening with said metal.

11. The method of claim 10, wherein said conductive barrier layer is formed on said protection layer inside of said via opening.

12. The method of claim 1, wherein forming said trench opening in said planarization material comprises forming a patterned etch mask above said planarization material.

13. The method of claim 1, wherein forming said trench opening in said planarization material comprises using said protection layer as an etch stop layer.

14. A method, comprising:

forming a layer of low-k dielectric material above a metallization layer of a semiconductor device;

forming via opening is said layer of low-k dielectric material and above a contact region formed in said metallization layer;

forming a protection layer above said semiconductor device, said protection layer covering an upper surface of said layer of low-k dielectric material and sidewall and bottom surfaces of said via opening;

forming a layer of planarization material above said semiconductor device, said layer of planarization material filling said via opening and covering said upper surface of said layer of low-k dielectric material;

forming an etch mask above said layer of planarization material;

forming trench opening in said etch mask and said layer of planarization material formed above said upper surface of said layer of low-k dielectric layer while removing a first portion of said planarization material from said via opening, wherein said trench opening is positioned above said via opening;

forming a trench in said layer of low-k dielectric layer using said trench opening as a mask; and

exposing said contact region in said metallization layer.

15. The method of claim 14, wherein said protection layer is formed on and in contact with at least said upper surface of said layer of low-k dielectric material and said sidewall surfaces of said via opening.

16. The method of claim 14, further comprising removing said protection layer from said sidewall and bottom surfaces of said via opening after forming said trench in said layer of low-k dielectric material.

17. The method of claim 14, further comprising forming a barrier layer inside of said trench and via openings.

18. The method of claim 17, wherein forming said barrier layer inside of said via opening comprises forming said barrier layer on at least said protection layer formed on said sidewalls of said via opening.

19. The method of claim 17, wherein forming said barrier layer inside of said via opening comprises forming said barrier layer on at least said exposed contact region.

20. The method of claim 14, further comprising filling said trench and via openings with a conductive material during a common material deposition process.

21. The method of claim 14, wherein forming said trench opening in said etch mask and said layer of planarization material comprises using said protection layer as an etch stop layer.