Test pad structure for reuse of interconnect level masks

• US 8,357,932 B2
• Filed: 03/25/2010
• Issued: 01/22/2013
• Est. Priority Date: 03/25/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: International Business Machines Corporation
• Inventors: Matusiewicz, Gerald
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US12/731,469
• Publication Number:
  US 20110233543A1
• Time in Patent Office: 1,034 Days
• Field of Search: None
• US Class Current: 257/48
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 1/44 Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
• CPC Class Codes: G03F 1/62 Pellicles, e.g. pellicle assemblies, e.g. having membrane on support frame; Preparation thereof
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

A test pad structure in a back-end-of-line metal interconnect structure is formed by repeated use of the same mask set, which includes a first line level mask, a first via level mask, a second line level mask, and a second via level mask. The test pad structure includes a two-dimensional array of test pads such that a first row is connected to a device macro structure in the same level, and test pads in another row are electrically connected to another device macro structure of the same design at an underlying level. The lateral shifting of electrical connection among pads located at different levels is enabled by lateral extension portions that protrude from pads and via structures that contact the lateral extension portions. This test pad structure includes more levels of testable metal interconnect structure than the number of used lithographic masks.

Claims

1. A structure comprising, from bottom to top:

a first line level structure including a first array of first metal pads, wherein a first lateral extension portion protrudes from each of said first metal pads;

a first via level structure including first metal vias, wherein each of said first metal vias contacts one of said first lateral extension portions;

a second line level structure including a second array of second metal pads, wherein a second lateral extension portion protrudes from each of said second metal pads, each of said lateral extension portion contacts one of said first metal vias, and a second metal pad among said second array of said second metal pads which vertically overlies a first metal pad among said first array of said first metal pads is electrically isolated from said first metal pad and is electrically connected to another first metal pad that does not directly underlie said second metal pad;

a first line level test structure including metallic structures located in a same level as said first line level structure, said first line level test structure including first metal lines electrically connected to two of said first metal pads; and

a second line level test structure including metallic structures located in a same level as said second line level structure, said second line level test structure including second metal lines electrically connected to two of said second metal pads.

2. The structure of claim 1, further comprising a second via level structure including second metal vias and located above said second line level structure, wherein each of said second metal vias contacts an upper surface of one of said second metal pads and does not contact any of said second lateral extension portions.

3. The structure of claim 2, further comprising a third line level structure including a third array of third metal pads, wherein a third lateral extension portion protrudes from each of said third metal pads, and each of said third lateral extension portions directly overlies one of said first lateral extension portions and each of said third metal pads directly overlies one of said first metal pads.

4. The structure of claim 3, wherein each two-dimensional shape of any structures within a level of said third line level structures directly overlies a congruent two-dimensional shape of a structure within a level of said first line level structures.

5. The structure of claim 3, further comprising a third via level structure including third metal vias, wherein each of said third metal vias contacts one of said third lateral extension portions.

6. The structure of claim 5, wherein each two-dimensional shape of any structures within a level of said third via level structures directly overlies a congruent two-dimensional shape of a structure within a level of said first via level structures.

7. The structure of claim 1, wherein said first line level structure, said first via level structure, and said second line level structure are embedded in at least one dielectric material layer located on at least one semiconductor device on a semiconductor substrate.

8. The structure of claim 1, wherein said first array of first metal pads and said second array of second metal pads are two-dimensional arrays with regular spacings in two horizontal directions, wherein each second metal pad in said second array directly overlies a first metal pad in said first array.

9. A method of forming a metal interconnect structure, said method comprising:

forming a first line level structure on a substrate, wherein said first line level structure comprises a first array of first metal pads embedded in a first dielectric layer, and a first lateral extension portion protrudes from each of said first metal pads;

forming a first via level structure and a second line level structure on said first line level structure, wherein said first via level structure comprises first metal vias embedded in a second dielectric layer, each of said first metal vias contacts one of said first lateral extension portions, said second line level structure comprises a second array of second metal pads embedded in said second dielectric layer, a second lateral extension portion protrudes from each of said second metal pads, each of said lateral extension portion contacts one of said first metal vias, and a second metal pad vertically overlying a first metal pad is electrically isolated from said first metal pad and is electrically connected to another first metal pad that does not directly underlie said second metal pad; and

forming a second via level structure including second metal vias embedded in a third dielectric layer on said second line level structure, wherein each of said second metal vias contacts an upper surface of one of said second metal pads and does not contact any of said second lateral extension portions.

10. The method of claim 9, further comprising forming a third line level structure including a third array of third metal pads embedded in said third dielectric layer, wherein a third lateral extension portion protrudes from each of said third metal pads, and each of said third lateral extension portion directly overlies one of said first lateral extension portions and each of said third metal pads directly overlies one of said first metal pads.

11. The method of claim 10, wherein each two-dimensional shape of any structures within a level of said third line level structures directly overlies a congruent two-dimensional shape of a structure within a level of said first line level structures.

12. The method of claim 10, further comprising forming a third via level structure including third metal vias in said third dielectric layer, wherein each of said third metal vias contacts one of said third lateral extension portions.

13. The method of claim 9, wherein said first array of first metal pads and said second array of second metal pads are formed as two-dimensional arrays with regular spacing in two horizontal directions, wherein each second metal pad in said second array directly overlies a first metal pad in said first array.

14. The method of claim 9, further comprising:

forming a first line level test structure including metallic structures located in a same level as said first line level structure, said first line level test structure comprising first metal lines electrically connected to two of said first metal pads; and

forming a second line level test structure including metallic structures located in a same level as said second line level structure, said second line level test structure comprising second metal lines electrically connected to two of said second metal pads.

15. A method of forming a metal interconnect structure, said method comprising:

forming a first line level structure on a substrate, wherein said first line level structure comprises a first array of first metal pads embedded in a first dielectric layer, and a first lateral extension portion protrudes from each of said first metal pads;

forming a first via level structure and a second line level structure on said first line level structure, wherein said first via level structure comprises first metal vias embedded in a second dielectric layer, each of said first metal vias contacts one of said first lateral extension portions, said second line level structure comprises a second array of second metal pads embedded in said second dielectric layer, a second lateral extension portion protrudes from each of said second metal pads, each of said lateral extension portion contacts one of said first metal vias, and a second metal pad vertically overlying a first metal pad is electrically isolated from said first metal pad and is electrically connected to another first metal pad that does not directly underlie said second metal pad;

forming a first line level test structure including metallic structures located in a same level as said first line level structure, said first line level test structure comprising first metal lines electrically connected to two of said first metal pads; and

forming a second line level test structure including metallic structures located in a same level as said second line level structure, said second line level test structure comprising second metal lines electrically connected to two of said second metal pads.

16. The method of claim 15, further comprising forming a second via level structure including second metal vias embedded in a third dielectric layer on said second line level structure, wherein each of said second metal vias contacts an upper surface of one of said second metal pads and does not contact any of said second lateral extension portions.

17. The method of claim 16, further comprising forming a third line level structure including a third array of third metal pads embedded in said third dielectric layer, wherein a third lateral extension portion protrudes from each of said third metal pads, and each of said third lateral extension portion directly overlies one of said first lateral extension portions and each of said third metal pads directly overlies one of said first metal pads.

18. The method of claim 17, wherein each two-dimensional shape of any structures within a level of said third line level structures directly overlies a congruent two-dimensional shape of a structure within a level of said first line level structures.

19. The method of claim 15, further comprising forming a third via level structure including third metal vias in said third dielectric layer, wherein each of said third metal vias contacts one of said third lateral extension portions.

20. The method of claim 15, wherein said first array of first metal pads and said second array of second metal pads are formed as two-dimensional arrays with regular spacing in two horizontal directions, wherein each second metal pad in said second array directly overlies a first metal pad in said first array.