Semiconductor device

• US 8,357,963 B2
• Filed: 07/19/2011
• Issued: 01/22/2013
• Est. Priority Date: 07/27/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Kato, Kiyoshi, Matsuzaki, Takanori
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): Oh, Jaehwan
• Application Number:
  US13/185,965
• Publication Number:
  US 20120025284A1
• Time in Patent Office: 553 Days
• Field of Search: 257/296, 257/297, 257/300, 257/547, 257/E29.28, 257/E29.296
• US Class Current: 257/297
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 41/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor device includes a material with which off-state current of a transistor can be sufficiently small; for example, an oxide semiconductor material is used. Further, transistors of memory cells of the semiconductor device, which include an oxide semiconductor material, are connected in series. Further, the same wiring (the j-th word line (j is a natural number greater than or equal to 2 and less than or equal to m)) is used as a wiring electrically connected to one of terminals of a capacitor of the j-th memory cell and a wiring electrically connected to a gate terminal of a transistor, in which a channel is formed in an oxide semiconductor layer, of the (j−1)-th memory cell. Therefore, the number of wirings per memory cell and the area occupied by one memory cell are reduced.

Claims

1. A semiconductor device comprising:

a source line;

a bit line;

(m+1) word lines (m is a natural number greater than or equal to

     2);

a selection line;

a first to an m-th memory cells connected in series between the source line and the bit line; and

a selection transistor including a gate terminal which is electrically connected to the selection line,

wherein each of the first to the m-th memory cells comprises;

a first transistor including a first gate terminal, a first source terminal, and a first drain terminal;

a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and

a capacitor,

the second transistor includes an oxide semiconductor layer,

a channel of the second transistor is formed in the oxide semiconductor layer,

the source line is electrically connected to the first source terminal of the m-th memory cell through the selection transistor,

the bit line is electrically connected to the second drain terminal of the first memory cell and the first drain terminal of the first memory cell,

a k-th word line (k is a natural number greater than or equal to 1 and less than or equal to m) is electrically connected to the second gate terminal of a k-th memory cell,

a (k+1)-th word line is electrically connected to one of terminals of the capacitor of the k-th memory cell,

the second drain terminal of a j-th memory cell (j is a natural number greater than or equal to 2 and less than or equal to m) is electrically connected to the first gate terminal of a (j−

1)-th memory cell, the second source terminal of the (j−

1)-th memory cell, and the other of the terminals of the capacitor of the (j−

1)-th memory cell,

the first gate terminal of the m-th memory cell, the second source terminal of the m-th memory cell, and the other of the terminals of the capacitor of the m-th memory cell are electrically connected to one another, and

the first drain terminal of the j-th memory cell is electrically connected to the first source terminal of the (j−

1)-th memory cell.

2. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region provided in a substrate including a semiconductor material other than an oxide semiconductor;

a pair of impurity regions between the channel formation region;

a first gate insulating layer over the channel formation region;

a first gate electrode over the first gate insulating layer to overlap the channel formation region; and

a first source electrode electrically connected to one of the pair of impurity regions, and a second drain electrode electrically connected to the other of the pair of impurity regions,

the first gate electrode corresponds to the first gate terminal,

the first source electrode corresponds to the first source terminal.

3. The semiconductor device according to claim 2, wherein the substrate including a semiconductor material other than an oxide semiconductor is a single crystal semiconductor substrate or an SOI substrate.

4. The semiconductor device according to claim 1,

wherein the first transistor comprises:

a channel formation region formed over an insulating surface and provided over the semiconductor layer that includes a semiconductor material other than an oxide semiconductor;

a pair of impurity regions between the channel formation region;

a first gate insulating layer overlapping the channel formation region;

a first gate electrode which overlaps the channel formation region with the first gate insulating layer provided between the first gate electrode and the channel formation region; and

a first source electrode electrically connected to one of the pair of impurity regions, and a second drain electrode electrically connected to the other of the pair of impurity regions,

the first gate electrode corresponds to the first gate terminal,

the first source electrode corresponds to the first source terminal.

5. The semiconductor device according to claim 1,

wherein the second transistor comprises:

a second source electrode and the second drain electrode that are electrically connected to the oxide semiconductor layer;

a second gate insulating layer; and

a second gate electrode which overlaps the oxide semiconductor layer with the second gate insulating layer provided between the oxide semiconductor layer and the second gate insulating layer,

the second source electrode corresponds to the second source terminal, and

the second drain electrode corresponds to the second drain terminal.

6. The semiconductor device according to claim 5, wherein the second drain electrode of the j-th memory cell and the second source electrode of the (j−

1)-th memory cell are formed using one conductive layer.

7. The semiconductor device according to claim 5, wherein the second drain electrode of the j-th memory cell, the second source electrode of the (j−

1)-th memory cell, and the other of the terminals of the capacitor of the (j−

1)-th memory cell are formed by using one conductive layer.

8. The semiconductor device according to claim 5, wherein the second drain electrode of the j-th memory cell, the second source electrode of the (j−

1)-th memory cell, the other of the terminals of the capacitor of the (j−

1)-th memory cell, and the first gate electrode of the (j−

1)-th memory cell are formed by using one conductive layer.

9. The semiconductor device according to claim 1, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga, and Zn.

10. The semiconductor device according to claim 1, wherein the semiconductor device is one selected from the group consisting of a laptop personal computer, a portable information terminal, an electronic book, a mobile phone, a digital camera and a television device.

11. A semiconductor device comprising:

a source line;

a bit line;

(m+1) word lines (m is a natural number greater than or equal to

     2);

a first selection line;

a second selection line;

a first to an m-th memory cells connected in series between the source line and the bit line;

a first selection transistor including a gate terminal which is electrically connected to the first selection line; and

a second selection transistor including a gate terminal which is electrically connected to the second selection line,

wherein each of the first to the m-th memory cells comprises;

a first transistor including a first gate terminal, a first source terminal, and a first drain terminal;

a second transistor including a second gate terminal, a second source terminal, and a second drain terminal; and

a capacitor,

the second transistor includes an oxide semiconductor layer,

a channel of the second transistor is formed in the oxide semiconductor layer,

the source line is electrically connected to the first source terminal of the m-th memory cell through the second selection transistor,

the bit line is electrically connected to the second drain terminal of the first memory cell and is electrically connected to the first drain terminal of the first memory cell through the first selection transistor,

a k-th word line (k is a natural number greater than or equal to 1 and less than or equal to m) is electrically connected to the second gate terminal of a k-th memory cell, and a (k+1)-th word line is electrically connected to one of terminals of the capacitor of the k-th memory cell,

the second drain terminal of a j-th memory cell (j is a natural number greater than or equal to 2 and less than or equal to in) is electrically connected to the first gate terminal of a (j−

1)-th memory cell, the second source terminal of the (j−

1)-th memory cell, and the other of the terminals of the capacitor of the (j−

1)-th memory cell,

the first gate terminal of the m-th memory cell, the second source terminal of the m-th memory cell, and the other of the terminals of the capacitor of the m-th memory cell are electrically connected to one another, and

the first drain terminal of the j-th memory cell is electrically connected to the first source terminal of the (j−

1)-th memory cell.

12. The semiconductor device according to claim 11,

wherein the first transistor comprises:

a channel formation region provided in a substrate including a semiconductor material other than an oxide semiconductor;

a pair of impurity regions between the channel formation region;

a first gate insulating layer over the channel formation region;

a first gate electrode over the first gate insulating layer to overlap the channel formation region; and

a first source electrode electrically connected to one of the pair of impurity regions, and a second drain electrode electrically connected to the other of the pair of impurity regions,

the first gate electrode corresponds to the first gate terminal,

the first source electrode corresponds to the first source terminal.

13. The semiconductor device according to claim 12, wherein the substrate including a semiconductor material other than an oxide semiconductor is a single crystal semiconductor substrate or an SOI substrate.

14. The semiconductor device according to claim 11,

wherein the first transistor comprises:

a channel formation region formed over an insulating surface and provided over the semiconductor layer that includes a semiconductor material other than an oxide semiconductor;

a pair of impurity regions between the channel formation region;

a first gate insulating layer overlapping the channel formation region;

a first gate electrode which overlaps the channel formation region with the first gate insulating layer provided between the first gate electrode and the channel formation region; and

a first source electrode electrically connected to one of the pair of impurity regions, and a second drain electrode electrically connected to the other of the pair of impurity regions,

the first gate electrode corresponds to the first gate terminal,

the first source electrode corresponds to the first source terminal.

15. The semiconductor device according to claim 11,

wherein the second transistor comprises:

a second source electrode and the second drain electrode that are electrically connected to the oxide semiconductor layer;

a second gate insulating layer; and

a second gate electrode which overlaps the oxide semiconductor layer with the second gate insulating layer provided between the oxide semiconductor layer and the second gate insulating layer,

the second source electrode corresponds to the second source terminal, and

the second drain electrode corresponds to the second drain terminal.

16. The semiconductor device according to claim 15, wherein the second drain electrode of the j-th memory cell and the second source electrode of the (j−

1)-th memory cell are formed using one conductive layer.

17. The semiconductor device according to claim 15, wherein the second drain electrode of the j-th memory cell, the second source electrode of the (j−

1)-th memory cell, and the other of the terminals of the capacitor of the (j−

1)-th memory cell are formed by using one conductive layer.

18. The semiconductor device according to claim 15, wherein the second drain electrode of the j-th memory cell, the second source electrode of the (j−

1)-th memory cell, the other of the terminals of the capacitor of the (j−

1)-th memory cell, and the first gate electrode of the (j−

1)-th memory cell are formed by using one conductive layer.

19. The semiconductor device according to claim 11, wherein the oxide semiconductor layer includes an oxide semiconductor material including In, Ga, and Zn.

20. The semiconductor device according to claim 11, wherein the semiconductor device is one selected from the group consisting of a laptop personal computer, a portable information terminal, an electronic book, a mobile phone, a digital camera and a television device.