Trench gate MOSFET and method of manufacturing the same

• US 8,357,971 B2
• Filed: 10/22/2008
• Issued: 01/22/2013
• Est. Priority Date: 10/29/2007
• Status: Active Grant

• Current Assignee: Nexperia B.V. (Wingtech Technology Co., Ltd.)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Peake, Steven Thomas, Rutter, Philip, Rogers, Christopher Martin, Drobnis, Miron, Butler, Andrew
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US12/739,341
• Publication Number:
  US 20100320532A1
• Time in Patent Office: 1,553 Days
• Field of Search: 257/330, 257/333, 257/E29.201, 257/E29.26
• US Class Current: 257/330
• CPC Class Codes: H01L 21/2251 Diffusion into or out of group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A Trench gate MOS field-effect transistor having a narrow, lightly doped, region extending from a channel accommodating region (3) of same conductivity type immediately adjacent the trench sidewall. The narrow region may be self-aligned to the top of a lower polysilicon shield region in the trench or may extend the complete depth of the trench. The narrow region advantageously relaxes the manufacturing tolerances, which otherwise require close alignment of the upper polysilicon trench gate to the body-drain junction.

Claims

1. A Trench field effect transistor (TrenchFET) comprising

a semiconductor body defining a first major surface,

a first and a second region of a first conductivity type,

a channel-accommodating third region therebetween of a second conductivity type opposite the first conductivity type,

a trench extending from the first major surface into the semiconductor body, adjacent the first and channel-accommodating third regions and extending into the second region,

a gate formed of electrically conducting material within the trench and spaced apart from the sidewalls and bottom of the trench,

a shield region formed of electrically conducting material within the trench and between the gate and bottom of the trench and spaced apart therefrom,

wherein the TrenchFET further comprises

a fourth region of the second conductivity type extending adjacent the sidewalls of the trench from the channel-accommodating third region towards the bottom of the trench, wherein the fourth region extends to a depth that is aligned to a top of the shield region, and wherein the fourth region is defined after the shield region is formed.

2. A TrenchFET according to claim 1, wherein the fourth region has a doping level which is lower than the doping level of the channel-accommodating third region.

3. A TrenchFET according to claim 1 wherein the fourth region has a width which is sufficiently small such that, in operation when the electrical potential of the gate creates a channel in the channel-accommodating third region, the fourth region is fully depleted.

4. A TrenchFET according to claim 1 wherein the fourth region has a width between 25 nm and 50 nm.

5. A TrenchFET according to claim 1 wherein the fourth region extends further from the first major surface than does the gate.

6. A TrenchFET according to claim 1 wherein the fourth region extends further from the first major surface than the shield region.

7. A TrenchFET according to claim 1 wherein the first conductivity type is n-type and the second conductivity type is p-type.

8. A method of manufacturing a TrenchFET comprising:

defining in a semiconductor body having a first major surface a first and a second region of a first conductivity type and a channel-accommodating third region of a second conductivity type opposite the first conductivity type therebetween,

defining a trench extending from the first major surface into the semiconductor body, adjacent the first and channel-accommodating third regions and extending into the second region,

forming a gate of electrically conducting material within the trench and spaced apart from the sidewalls and bottom of the trench,

forming a shield region of electrically conducting material within the trench and between the gate and bottom of the trench and spaced apart therefrom,

wherein the method further comprises,

defining a fourth region of the second conductivity type adjacent the sidewalls of the trench and extending from the channel-accommodating third region towards the bottom of the trench, wherein defining the fourth region includes self-aligning the fourth region to the top of the shield, and wherein the fourth region is defined after the step of forming the shield region.

9. A method as claimed in claim 8, wherein the fourth region is defined by an angled implant.

10. A method as claimed in claim 8, wherein the fourth region is defined by gaseous vapour phase deposition.

11. A method as claimed in claim 8, wherein the fourth region is defined after the step of defining the trench and before a step of defining a thick oxide layer in the bottom of the trench.