Low cost high density rectifier matrix memory

• US 8,358,525 B2
• Filed: 10/05/2010
• Issued: 01/22/2013
• Est. Priority Date: 06/22/2000
• Status: Expired due to Fees

• Current Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Original Assignee: Contour Semiconductor, Inc.
• Inventors: Shepard, Daniel R.
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US12/898,205
• Publication Number:
  US 20110019455A1
• Time in Patent Office: 840 Days
• Field of Search: 365/51, 365/163, 365/113, 365/230.06, 438/95
• US Class Current: 365/51
• CPC Class Codes: G06K 5/04 Verifying the alignment of markings
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 27/10 including a plurality of individual components in a repetitive configuration
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A high density memory device is fabricated three dimensionally in layers. To keep points of failure low, address decoding circuits are included within each layer so that, in addition to power and data lines, only the address signal lines need be interconnected between the layers.

Claims

1. An electronic memory device comprising:

a substrate; and

disposed above the substrate, a plurality of layers of memory circuitry defining a memory array, each layer of memory circuitry comprising a plurality of storage locations,

wherein (i) the memory array is organized as a plurality of individually enableable sub-arrays, and (ii) the substrate comprises at least one of address decoding logic, row and column selection logic, a line driver-amplifier, or a sense amplifier.

2. The electronic memory device of claim 1, wherein, during operation, at least one of the sub-arrays is enabled and at least one of the sub-arrays is not enabled.

3. The electronic memory device of claim 1, wherein each of the plurality of layers corresponds to a sub-array.

4. The electronic memory device of claim 1, wherein the substrate comprises a semiconductor material.

7. An electronic memory device of claim 1 comprising:

a substrate; and

disposed above the substrate, a plurality of layers of memory circuitry defining a memory array, each layer of memory circuitry comprising a plurality of storage locations,

wherein (i) the memory array is organized as a plurality of individually enableable sub-arrays, and (ii) the substrate consists essentially of an insulating material.

8. An electronic memory device of claim 1 comprising:

a substrate; and

disposed above the substrate, a plurality of layers of memory circuitry defining a memory array, each layer of memory circuitry comprising a plurality of storage locations,

wherein (i) the memory array is organized as a plurality of individually enableable sub-arrays, and (ii) the substrate comprises a plurality of memory controllers.

5. An electronic memory device comprising:

a substrate; and

disposed above the substrate, a plurality of layers of memory circuitry defining a memory array, each layer of memory circuitry comprising a plurality of storage locations,

wherein (i) the memory array is organized as a plurality of individually enableable sub-arrays, and (ii) the substrate comprises at least one of error detection and correction logic, data decryption logic, data encryption logic, data compression logic, or data decompression logic.

6. An electronic memory device of comprising:

a substrate; and

disposed above the substrate, a plurality of layers of memory circuitry defining a memory array, each layer of memory circuitry comprising a plurality of storage locations,

wherein (i) the memory array is organized as a plurality of individually enableable sub-arrays, and (ii) each sub-array is individually powered.