Simulating a different number of memory circuit devices
First Claim
Patent Images
1. An apparatus, comprising:
- an interface circuit operable to communicate with a first number of separate physical memory circuit devices and a system,wherein the interface circuit is operable to;
present to the system a second number of simulated memory circuit devices such that the first number of physical memory circuit devices appear to the system as the second number of simulated memory circuit devices, wherein presenting the simulated memory circuit devices to the system includes simulating one or more mode register operation control signals, and wherein the second number is less than the first number;
receive, from the system, address or control signals sent to the second number of simulated memory circuit devices for performing one or more operations on the second number of simulated memory circuit devices;
communicate the address or control signals to the first number of memory circuit devices;
present to the system a first column address strobe (CAS) latency associated with each simulated memory circuit device, wherein the first CAS latency is a higher value than a second CAS latency associated with each physical memory circuit device;
receive, from a memory controller of the system, write commands sent to the second number of simulated memory circuit devices; and
delay communicating the write commands to the first number of physical memory circuit devices by an amount of time equal to the difference between the first CAS latency and the second CAS latency.
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Abstract
A system and method are provided for simulating a different number of memory circuits. Included is an interface circuit in communication with a first number of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one memory circuit of a second number. Further, the interface circuit interfaces a majority of address or control signals of the memory circuits.
880 Citations
39 Claims
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1. An apparatus, comprising:
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an interface circuit operable to communicate with a first number of separate physical memory circuit devices and a system, wherein the interface circuit is operable to; present to the system a second number of simulated memory circuit devices such that the first number of physical memory circuit devices appear to the system as the second number of simulated memory circuit devices, wherein presenting the simulated memory circuit devices to the system includes simulating one or more mode register operation control signals, and wherein the second number is less than the first number; receive, from the system, address or control signals sent to the second number of simulated memory circuit devices for performing one or more operations on the second number of simulated memory circuit devices; communicate the address or control signals to the first number of memory circuit devices; present to the system a first column address strobe (CAS) latency associated with each simulated memory circuit device, wherein the first CAS latency is a higher value than a second CAS latency associated with each physical memory circuit device; receive, from a memory controller of the system, write commands sent to the second number of simulated memory circuit devices; and delay communicating the write commands to the first number of physical memory circuit devices by an amount of time equal to the difference between the first CAS latency and the second CAS latency. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. A method, comprising:
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presenting to a system a first number of simulated memory circuit devices; receiving, from the system, address or control signals sent to the first number of simulated memory circuit devices; communicating the address or control signals to a second number of separate physical memory circuit devices, wherein the first number is less than the second number, and wherein presenting the simulated memory circuit devices to the system includes simulating one or more control signals including one or more mode register operations; presenting to the system a first column address strobe (CAS) latency associated with each simulated memory circuit device, wherein the first CAS latency is a higher value than a second CAS latency associated with each physical memory circuit device; receiving, from a memory controller of the system, write commands sent to the first number of simulated memory circuit devices; and delaying communicating the write commands to the second number of separate physical memory circuit devices by an amount of time equal to the difference between the first CAS latency and the second CAS latency. - View Dependent Claims (34, 35, 36)
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37. A memory module, comprising:
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a first number of separate physical memory circuit devices; and an interface circuit operable to; interface the first number of physical memory circuit devices and a system in order to present to the system a second number of simulated memory circuit devices, wherein the second number is less than the first number, and wherein presenting to the system the second number of simulated memory circuit devices includes simulating one or more mode register operation control signals; receive, from the system, address or control signals sent to the second number of simulated memory circuit devices; communicate the address or control signals to the first number of physical memory circuit devices; present to the system a first column address strobe (CAS) latency associated with each simulated memory circuit device, wherein the first CAS latency is a higher value than a second CAS latency associated with each physical memory circuit device; receive, from a memory controller of the system, write commands sent to the second number of simulated memory circuit devices; and delay communicating the write commands to the first number of physical memory circuit devices by an amount of time equal to the difference between the first CAS latency and the second CAS latency. - View Dependent Claims (38, 39)
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Specification