Method and apparatus for signaling between devices of a memory system

• US 8,359,445 B2
• Filed: 01/27/2009
• Issued: 01/22/2013
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Tsern, Ely K., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): NGUYEN, THAN VINH
• Application Number:
  US12/360,780
• Publication Number:
  US 20090138646A1
• Time in Patent Office: 1,456 Days
• Field of Search: None
• US Class Current: 711/167
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A method and apparatus for signaling between devices of a memory system is provided. In accordance with an embodiment of the invention, one or more of several capabilities are implemented to provide heretofore unattainable levels of important system metrics, for example, high performance and/or low cost. These capabilities relate to timing adjustment capabilities, bit time adjustment capabilities, cycle time selection, use of differential and/or non-differential signaling for bus signals and/or clock signals, use of termination structures on a bus, including integrated termination structures, and active control circuitry to allow adjustment to different characteristic bus impedances and power-state control, including a calibration process to optimize the termination value, use of slew rate control circuitry and transfer characteristic control circuitry in the predriver and driver of transmitter blocks to allow adjustment to different characteristic bus impedances and to allow adjustment for other bus properties, including a calibration process to optimize the such circuitry, and/or provision of a memory component designed to prefetch (preaccess) words that are wider than the width of the data bus so that the memory access bandwidth approximately matches the transfer bandwidth, and memory component able to adjust the size of the prefetch (preaccess) word to accommodate connection to data buses of different width.

Claims

1. A memory system comprising:

a memory controller;

a plurality of memory components;

a control bus coupled to the memory controller and coupled to each memory component of the plurality of memory components at a different point along its length such that respective, different times are required for control information to propagate on the control bus from the memory controller to each memory component of the plurality of memory components;

a plurality of dedicated differential data signaling paths coupled to the memory controller, each dedicated differential data signaling path of the plurality of dedicated differential data signaling paths coupled respectively to a memory component of the plurality of memory components; and

wherein the memory controller includes circuitry to transmit respective differential data signals to the plurality of memory components via the plurality of dedicated differential data signaling paths after delaying by respective, different time intervals to at least account for the respective, different times required for the control information to propagate on the control bus from the memory controller to each respective memory component of the plurality of memory components.

2. The memory system of claim 1 wherein a bit time interval of the respective differential data signals propagating on the plurality of dedicated differential data signaling paths is shorter than a bit time interval of the control information propagating on the control bus.

3. The memory system of claim 1 wherein each memory component of the plurality of memory components comprises a respective termination structure coupled to each respective differential data signaling path of the plurality of dedicated differential data signaling paths.

4. The memory system of claim 3 wherein a bit time interval of the respective differential data signals propagating on the plurality of dedicated differential data signaling paths is shorter than a bit time interval of the control information propagating on the control bus.

5. The memory system of claim 3 wherein the memory controller comprises a plurality of termination structures coupled respectively to the plurality of dedicated differential data signaling paths.

6. The memory system of claim 1 wherein the control bus uses non-differential signaling.

7. The memory system of claim 1 wherein each of the respective, different time intervals corresponds to at least a time difference between the time required for the control information to propagate on the control bus from the memory controller to a respective memory component of the plurality of memory components and a time required for a respective one of the differential data signals to propagate on its respective differential data signaling path from the memory controller to the respective memory component.

8. The memory system of claim 1 wherein the circuitry to transmit respective differential data signals to the plurality of memory components via the plurality of dedicated differential data signaling paths after delaying by respective, different time intervals comprises a plurality of phase offset selection circuits, each phase offset selection circuit of the plurality of phase offset selection circuits to select a clock signal of a plurality of phase-distributed clock signals to be a timing reference for transmitting data onto a respective one of the dedicated differential data signaling paths of the plurality of dedicated differential data signaling paths.

9. The memory system of claim 1 further comprising a clock signal path coupled to each of the memory components at a different point along its length such that respective, different times are required for a clock signal to propagate on the clock signal path from the memory controller to each memory component of the plurality of memory components, wherein the plurality of memory components receives the clock signal propagating on the clock signal path and wherein each memory component of the plurality of memory components samples the control information propagating on the control bus synchronously with respect to the clock signal.

10. The memory system of claim 9, wherein the time required for the control information to propagate on the control bus from the memory controller to a respective memory component of the plurality of memory components is at least a time that lapses between the control information being transmit by the memory controller, onto the control bus, and the respective memory component sampling the control information synchronously with respect to the clock signal, and

wherein the circuitry to transmit the differential data signals by respective, different time intervals, compensates for the different times required for the clock signal to propagate on the clock signal path to each memory component of the plurality of memory components.

11. The memory system of claim 9 wherein a first time is required for the control information to propagate on the control bus from the memory controller to a first memory component of the plurality of memory components and a second time is required for the control information to propagate on the control bus from the memory controller to a second memory component of the plurality of the memory components, and wherein a difference between the first time and the second time exceeds a period of the clock signal.

12. The memory system of claim 9 wherein each bit of the control information is valid at an input of each of the memory components for a bit time interval that corresponds to a predetermined fraction of the period of the clock signal.

13. The memory system of claim 12 wherein a first time is required for the control information to propagate on the control bus from the memory controller to a first memory component of the plurality of memory components and a second time is required for the control information to propagate on the control bus from the memory controller to a second memory component of the plurality of the memory components, and wherein a difference between the first time and the second time exceeds a period of the clock signal.

14. The memory system of claim 9 wherein two serial bits of control information are output from the memory controller onto the control bus during a cycle of the clock signal and wherein eight serial bits of data are output from at least one of the memory components of the plurality of memory components onto the respective dedicated differential data signaling path during a cycle of the clock signal.

15. The memory system of claim 9 wherein at least two serial bits of data are output from at least one of the plurality of memory components onto the respective dedicated differential data signaling path during a cycle of the clock signal, and wherein a signaling rate on the control bus is lower than a signaling rate on a dedicated differential data signaling path of the plurality of dedicated differential data signaling paths.

16. The memory system of claim 1 further comprising a plurality of dedicated timing signal paths coupled to the memory controller and coupled respectively to the plurality of memory components, the dedicated timing signal paths to convey respective timing signals from the memory controller to the plurality of memory components to indicate respective times at which the differential data signals are to be sampled within the plurality of memory components.

17. The memory system of claim 16 wherein the respective timing signals are strobe signals.

18. A memory controller comprising:

control transmit circuitry to transmit control information to a plurality of memory components via a control bus, the control bus being coupled to each memory component of the plurality of memory components at a different point along its length such that respective times required for the control information to propagate from the memory controller to each memory component of the plurality of memory components are different;

dedicated differential data transmit circuitry to transmit differential data signals to the plurality of memory components via respective differential data signaling paths; and

timing circuitry to delay transmission of the respective differential data signals on each of the differential data signaling paths by a respective time interval that is based, at least in part, on the time required for the control information to propagate on the control bus from the memory controller to each respective memory component of the plurality of memory components.

19. The memory controller of claim 18 wherein the respective time interval corresponds to a time difference between the time required for the control information to propagate on the control bus from the memory controller to the respective memory component and a time required for the differential data signal to propagate on the differential data signaling path from the memory controller to the respective memory component.

20. The memory controller of claim 18 wherein the timing circuitry comprises a plurality of phase offset selection circuits, each phase offset selection circuit of the plurality of phase offset selection circuits to select a clock signal of a plurality of phase-distributed clock signals to be a timing reference for transmitting data onto a respective one of the differential data signaling paths.

21. The memory controller of claim 20 further comprising clock generation circuitry to generate the plurality of phase-distributed clock signals, the plurality of phase-distributed clock signals having phase offsets that are substantially evenly distributed within a cycle time of a first clock signal.

22. The memory controller of claim 21 wherein the clock generation circuitry comprises a phase-locked loop circuit to generate the first clock signal based on a reference clock signal that has a lower frequency than the first clock signal.

23. The memory controller of claim 21 wherein each phase offset selection circuit of the plurality of phase offset selection circuits comprises a multiplexer to select the clock signal of the plurality of phase-distributed clock signals.

24. The memory controller of claim 18 further comprising a buffer to provide a clock signal to a clock signal path coupled to each of the memory components at a different point along its length such that respective times required for the clock signal to propagate to each memory component of the plurality of memory components are different, wherein the plurality of memory components receives the clock signal propagating on the clock signal path, wherein each memory component of the plurality of memory components samples the control information propagating on the control bus synchronously with respect to the clock signal, wherein the timing circuitry to delay transmission of the respective differential data signals by respective, different time intervals, compensates for the different times required for the clock signal to propagate on the clock signal path to each memory component of the plurality of memory components.

25. The memory controller of claim 24, wherein the time required for the control information to propagate on the control bus from the memory controller to a respective memory component of the plurality of memory components is at least a time that lapses between the control information being transmit by the memory controller, onto the control bus, and the respective memory component sampling the control information synchronously with respect to the clock signal.

26. The memory controller of claim 24 wherein a first time is required for the control information to propagate on the control bus from the memory controller to a first memory component of the plurality of memory components and a second time is required for the control information to propagate on the control bus from the memory controller to a second memory component of the plurality of the memory components, and wherein a difference between the first time and the second time exceeds a period of the clock signal.

27. The memory controller of claim 18 further comprising a plurality of dedicated timing signal paths coupled to the memory controller and coupled respectively to the plurality of memory components, the dedicated timing signal paths to convey respective timing signals to the plurality of memory components to indicate respective times at which the differential data signals are to be sampled within the plurality of memory components.

28. The memory controller of claim 27 wherein the respective timing signals are strobe signals.

29. The memory controller of claim 27 wherein the respective timing signals are clock signals.

30. A method of controlling memory components in a system that includes at least a first memory component and a second memory component, the method comprising:

transmitting control information to the first and second memory components via a control bus, wherein the control information propagates past the first memory component and the second memory component in sequence, and wherein a first propagation time required for the control information to propagate on the control bus to the first memory component is different from a second propagation time required for the control information to propagate on the control bus to the second memory component;

transmitting a first differential data signal to the first memory component via a first dedicated differential data signaling path after delaying for a first time interval, wherein the first time interval is based at least in part on the first propagation time; and

transmitting a second differential data signal to the second memory component via a second dedicated differential data signaling path after delaying for a second time interval, wherein the second time interval is based at least in part on the second propagation time.

31. The method of claim 30 wherein transmitting the first differential data signal to the first memory component via the first dedicated differential data signaling path after delaying for a first time interval comprises delaying transmission of the first differential data signal according to a difference between the first propagation time and a time required for the first differential data signal to propagate to the first memory component via the first dedicated differential data signaling path.

32. The method of claim 31 wherein transmitting the second differential data signal to the second memory component via the second dedicated differential data signaling path after delaying for the second time interval comprises delaying transmission of the second differential data signal according to a difference between the second propagation time and a time required for the second differential data signal to propagate to the second memory component via the second dedicated differential data signaling path.

33. The method of claim 31 wherein transmitting the first differential data signal to the first memory component via the first dedicated differential data signaling path after delaying for the first time interval comprises selecting a transmit clock signal from a plurality of phase-distributed clock signals such that the transmit clock signal includes a phase offset that corresponds to the first time interval.

34. The method of claim 33 further comprising generating the plurality of phase-distributed clock signals in a phase-locked loop circuit.

35. A memory controller for controlling memory components in a system that includes at least a first memory component and a second memory component, the memory controller comprising:

means for transmitting control information to the first and second memory components via a control bus, wherein the control information propagates past the first memory component and the second memory component in sequence, and wherein a first propagation time required for the control information to propagate on the control bus to the first memory component is different from a second propagation time required for the control signal to propagate on the control bus to the second memory component;

means for transmitting a first differential data signal to the first memory component via a first dedicated differential data signaling path after delaying for a first time interval, wherein the first time interval is based at least in part on the first propagation time; and

means for transmitting a second differential data signal to the second memory component via a second dedicated differential data signaling path after delaying for a second time interval, wherein the second time interval is based at least in part on the second propagation time.