Pixel designs of improving the aperture ratio in an LCD

• US 8,361,821 B2
• Filed: 04/10/2012
• Issued: 01/29/2013
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Lin, Hsiang-Lin, Lin, Ching-Huan, Shih, Chih-Hung, Huang, Wei-Ming
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): POMPEY, RON EVERETT
• Application Number:
  US13/443,672
• Publication Number:
  US 20120196392A1
• Time in Patent Office: 294 Days
• Field of Search: 438/34, 438/30, 438/158, 438/258, 438/266, 257/E21.159, 257/E21.166, 257/E21.414, 349/139, 349/44
• US Class Current: 438/30
• CPC Class Codes: G02F 1/13606 having means for reducing parasitic capacitance
• CPC Class Codes: G02F 1/136209 Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 1/136286 Wiring, e.g. gate line, drain line
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors

Abstract

In one aspect of this invention, a pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode having a first portion and a second portion extending from the first portion, and formed over the scan line, the data line and the switch, where the first portion is overlapped with the switch and the second portion is overlapped with the data line, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode in the pixel area, where the first portion is overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween and the second portion has no overlapping with the second portion of the shielding electrode.

Claims

1. A method for fabricating a pixel structure, comprising the steps of:

(a) providing a substrate;

(b) forming a scan line and a gate electrode on the substrate, wherein the gate electrode is electrically connected to the scan line;

(c) forming a first insulation layer on the substrate, overlying the scan line and the gate electrode;

(d) forming a semiconductor layer on the first insulation layer, wherein the semiconductor layer is overlapped with the gate electrode;

(e) forming a source electrode and a drain electrode on the semiconductor layer and a data line on the first insulation layer, respectively, wherein the source electrode is electrically connected to the data line, and wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode define a switch;

(f) forming a second insulation layer on the first insulation layer, overlying the data line and the switch;

(g) forming a shielding electrode on the second insulation layer, wherein the shielding electrode has a first portion overlapped with the switch, and a second portion extending from the first portion and overlapped with the data line;

(h) forming a third insulation layer on the second insulation layer, overlying the shielding electrode; and

(i) forming a pixel electrode on the third insulation layer, wherein the pixel electrode has a first portion overlapped with the first portion of the shielding electrode so as to define a storage capacitor therebetween, and a second portion extending from the first portion having no overlapping with the second portion of the shielding electrode,

wherein the source electrode and the drain electrode of the switch are electrically connected to the data line and the pixel electrode respectively.

2. The method of claim 1, wherein the step of forming the semiconductor layer comprises the steps of:

(a) forming a channel layer on the first insulation layer;

(b) forming an ohmic contact layer on the channel layer; and

(c) patterning the channel layer and the ohmic contact layer to form the semiconductor layer forming the source electrode and the drain electrode.

3. The method of claim 2, wherein the channel layer is formed of amorphous silicon (a-Si), and wherein the ohmic contact layer is formed of an N⁺ doped or CVD deposited semiconductor.

4. The method of claim 2, wherein the ohmic contact layer is patterned to have a first portion and a second portion separated from the first portion, and the source electrode and drain electrode are substantially in contact with the first portion and the second portion of the ohmic contact layer, respectively.

5. The method of claim 1, wherein the shielding electrode comprises an opaque, conductive material.

6. The method of claim 1, wherein the pixel electrode has a comb-like shape.

7. The method of claim 1, wherein the pixel electrode is made of a transparent, conductive material.