Embedded wafer-level bonding approaches

• US 8,361,842 B2
• Filed: 09/13/2010
• Issued: 01/29/2013
• Est. Priority Date: 07/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Lin, Jing-Cheng
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US12/880,736
• Publication Number:
  US 20120028411A1
• Time in Patent Office: 869 Days
• Field of Search: 257/E21.499, 257/E21.502, 257/E21.503, 438/107, 438/110, 438/118, 438/126, 438/127, 438/678
• US Class Current: 438/118
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2224/0233 Structure of the redistribution layers
• CPC Class Codes: H01L 2224/02333 being a bump
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/11002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/11334 using preformed bumps
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 2224/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A method includes providing a carrier with an adhesive layer disposed thereon; and providing a die including a first surface, a second surface opposite the first surface. The die further includes a plurality of bond pads adjacent the second surface; and a dielectric layer over the plurality of bond pads. The method further includes placing the die on the adhesive layer with the first surface facing toward the adhesive layer and dielectric layer facing away from the adhesive layer; forming a molding compound to cover the die, wherein the molding compound surrounds the die; removing a portion of the molding compound directly over the die to expose the dielectric layer; and forming a redistribution line above the molding compound and electrically coupled to one of the plurality of bond pads through the dielectric layer.

Claims

1. A method comprising:

providing a carrier with an adhesive layer disposed thereon;

providing a die comprising a substrate, a plurality of bond pads over the substrate, a dielectric layer over the plurality of bond pads, and a plurality of metal pillars in the dielectric layer and connected to the plurality of bond pads, wherein the dielectric layer comprises a top portion covering the plurality of metal pillars;

placing the die on the adhesive layer;

forming a molding compound to cover the die and the top portion of the dielectric layer, wherein the molding compound surrounds the die;

removing a portion of the molding compound over the die and the top portion of the dielectric layer to expose the plurality of metal pillars; and

forming a redistribution line above the dielectric layer and electrically coupled to the plurality of metal pillars.

2. The method of claim 1, wherein during the step of forming the redistribution line, the metal pillars are used as alignment marks.

3. The method of claim 1, wherein the step of removing the portion of the molding compound comprises performing a chemical mechanical polish (CMP) on the molding compound.

4. The method of claim 1 further comprising, after the step of forming the redistribution line, forming a metal bump over and electrically coupled to the redistribution line.

5. The method of claim 1 further comprising demounting the carrier.

6. The method of claim 1, wherein a thickness of the dielectric layer is greater than about 10 μ

m.

7. A method comprising:

providing a carrier with an adhesive layer disposed thereon;

providing a plurality of dies, with each of the plurality of dies comprising;

a substrate;

a plurality of bond pads over the substrate;

a dielectric layer over the plurality of bond pads; and

a plurality of metal pillars in the dielectric layer and electrically coupled to the plurality of bond pads, wherein in each of the plurality of dies, the dielectric layer comprises a top portion over top surfaces of the plurality of metal pillars;

placing the plurality of dies on the adhesive layer with a bottom of the substrate of each of the plurality of dies facing the adhesive layer;

filling a molding compound between the plurality of dies, wherein the molding compound covers the dielectric layer of each of the plurality of dies, wherein substantially entireties of all gaps between the plurality of dies are filled with the molding compound;

performing a planarization on the molding compound until the plurality of metal pillars are exposed, wherein in the step of planarization, the top portion of the dielectric layer is removed, and the plurality of metal pillars are exposed; and

forming redistribution lines over and electrically coupled to the plurality of metal pillars.

8. The method of claim 7, wherein before the step of performing the planarization, top surfaces of the metal pillars are substantially level with a top surface of the dielectric layer.

9. The method of claim 7, wherein before the step of performing the planarization, top surfaces of the metal pillars are below a top surface of the dielectric layer.

10. The method of claim 7, wherein the dielectric layer comprises a non-molding-compound dielectric material.

11. The method of claim 7, wherein the dielectric layer comprises a molding compound.

12. The method of claim 7, wherein the redistribution lines extend directly over the molding compound.

13. The method of claim 7 further comprising:

after the step of forming the redistribution lines, forming a metal bump over and electrically coupled to one of the redistribution lines; and

removing the carrier from the plurality of dies and the molding compound.

14. The method of claim 7, wherein after the step of filling the molding compound, the molding compound extends continuously from one edge of one of the plurality of dies to an edge of a neighboring one of the plurality of dies.