Precise resistor on a semiconductor device
First Claim
Patent Images
1. A method of making an integrated circuit, the method comprising:
- forming a polysilicon layer on a substrate;
patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate;
forming a protective layer over the polysilicon gate;
performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the protective layer during performance of the first ion implantation;
performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and
performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion.
1 Assignment
0 Petitions
Accused Products
Abstract
A method includes forming a polysilicon layer on a substrate; and patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate. A first ion implantation is performed on the polysilicon resistor to adjust electric resistance of the polysilicon resistor. A second ion implantation is performed on a top portion of the polysilicon resistor such that the top portion of the polysilicon resistor has an enhanced etch resistance. An etch process is then used to remove the polysilicon gate while the polysilicon resistor is protected by the top portion.
-
Citations
20 Claims
-
1. A method of making an integrated circuit, the method comprising:
-
forming a polysilicon layer on a substrate; patterning the polysilicon layer to form a polysilicon resistor and a polysilicon gate; forming a protective layer over the polysilicon gate; performing a first ion implantation to the polysilicon layer to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the protective layer during performance of the first ion implantation; performing a second ion implantation to a top portion of the polysilicon resistor such that the top portion has an enhanced etch resistance; and performing an etch process to remove the polysilicon gate while the polysilicon resistor is protected by the implanted top portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
-
-
12. A method comprising:
-
forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate; performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by a first patterned material layer during performance of the first ion implantation; performing a second ion implantation to the polysilicon gate to form source and drain regions in the semiconductor substrate that are adjacent the polysilicon gate, wherein the polysilicon resistor is covered by a second patterned material layer during performance of the second ion implantation; and performing a third ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by a third patterned material layer during performance of the third ion implantation. - View Dependent Claims (13, 14, 15, 16, 17, 18)
-
-
19. A method comprising:
-
forming a polysilicon resistor and a polysilicon gate on a semiconductor substrate; forming a first patterned material layer over the polysilicon gate; performing a first ion implantation to the polysilicon resistor to adjust electric resistance of the polysilicon resistor, wherein the polysilicon gate is covered by the first patterned material layer during performance of the first ion implantation; forming a second patterned material layer over the polysilicon gate, the second patterned material layer being different than the first patterned material layer; and after forming the second patterned material layer over the polysilicon gate, performing a second ion implantation to the polysilicon resistor such that a top portion of the polysilicon resistor has an enhanced etch resistance, wherein the polysilicon gate is covered by the second patterned material layer during performance of the second ion implantation. - View Dependent Claims (20)
-
Specification