Embedded DRAM with multiple gate oxide thicknesses
First Claim
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1. A method of forming a DRAM cell having an access transistor and a capacitor structure, the method comprising:
- forming a field dielectric in a semiconductor substrate having a first conductivity type, wherein the field dielectric extends below an upper surface of the semiconductor substrate;
providing a first mask on an upper surface of the semiconductor substrate thereby exposing a capacitor region;
ion implanting an impurity into a first portion of the semiconductor substrate;
removing the first mask;
providing a second mask on the upper surface of the semiconductor substrate to expose the capacitor region and a logic transistor;
removing oxide portions of the capacitor region and logic transistor;
removing the second mask; and
forming an oxide layer on the upper surface of the semiconductor substrate to produce an oxide layer in the capacitor region that is greater in thickness than an oxide of the logic transistor, and less than the thickness of an oxide of the access transistor.
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Abstract
A method of forming an embedded DRAM cell having multiple-thickness gate dielectrics. An oxidation-enhancing dopant is selectively implanted into a well region in an area that is exposed by a first mask. A thermal oxidation step simultaneously produces the field dielectric for two distinct devices each having a different oxide thickness. The method is applicable to quad-density DRAM cells using fewer oxidation steps. The method is also applicable to planar DRAM cells, and does not require increasing the number of masks during the fabrication of planar DRAM cells.
29 Citations
24 Claims
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1. A method of forming a DRAM cell having an access transistor and a capacitor structure, the method comprising:
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forming a field dielectric in a semiconductor substrate having a first conductivity type, wherein the field dielectric extends below an upper surface of the semiconductor substrate; providing a first mask on an upper surface of the semiconductor substrate thereby exposing a capacitor region; ion implanting an impurity into a first portion of the semiconductor substrate; removing the first mask; providing a second mask on the upper surface of the semiconductor substrate to expose the capacitor region and a logic transistor; removing oxide portions of the capacitor region and logic transistor; removing the second mask; and forming an oxide layer on the upper surface of the semiconductor substrate to produce an oxide layer in the capacitor region that is greater in thickness than an oxide of the logic transistor, and less than the thickness of an oxide of the access transistor. - View Dependent Claims (2)
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3. A method of forming a dynamic random access memory (DRAM) cell in a semiconductor substrate comprising:
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fabricating a storage capacitor of the DRAM cell with a thin gate dielectric layer; and fabricating an access transistor of the DRAM cell with a thicker dielectric layer having a thickness greater than the thin gate dielectric layer, wherein a dopant is selectively implanted in an area that will constitute the storage capacitor to form to thin gate dielectric layer. - View Dependent Claims (4, 5, 6, 7, 8)
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9. A method comprising:
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defining an access transistor region, a capacitor region, a logic region and an input/output (I/O) region in a semiconductor region having a first conductivity type; and fabricating an access transistor of a dynamic random access memory (DRAM) cell in the access transistor region, a capacitor of the DRAM cell in the capacitor region, a logic transistor in the logic region, and an I/O transistor in the I/O region, wherein the fabricating includes; implanting an impurity having a second conductivity type, opposite the first conductivity type, into the capacitor region; performing a first thermal oxidation step, thereby simultaneously forming first oxide layers in the access transistor region, the capacitor region, the logic region and the I/O region; removing the first oxide layers formed in the capacitor region and the logic region, but not removing the first oxide layers formed in the access transistor region and the I/O region; and
thenperforming a second thermal oxidation step, thereby simultaneously increasing thicknesses of the first oxide layers in the access transistor region and the I/O region, and forming second oxide layers in the capacitor region and the logic region. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A method comprising:
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defining an access transistor region and a capacitor region, which is continuous with the access transistor region, in a semiconductor region having a first conductivity type; defining a logic region in the semiconductor region, wherein the logic region is isolated from the access transistor region and the capacitor region; defining an input/output (I/O) region in the semiconductor region, wherein the I/O region is isolated from the logic region, the access transistor region and the capacitor region; implanting an impurity having a second conductivity type, opposite the first conductivity type, into the capacitor region; simultaneously forming a first oxide layer in the access transistor region, the capacitor region, the logic region and the I/O region; removing portions of the first oxide layer formed in the capacitor region and the logic region, but not removing portions of the first oxide layer formed in the access transistor region and the I/O region; and
thensimultaneously forming a second oxide layer in the access transistor region, the capacitor region, the logic region and the I/O region. - View Dependent Claims (22, 23, 24)
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Specification