Semiconductor device and manufacturing method thereof

• US 8,362,478 B2
• Filed: 04/13/2010
• Issued: 01/29/2013
• Est. Priority Date: 04/16/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Godo, Hiromichi, Kishida, Hideyuki
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US12/759,220
• Publication Number:
  US 20100264412A1
• Time in Patent Office: 1,022 Days
• Field of Search: 257/43, 257/66, 257/72, 257/E29.095
• US Class Current: 257/43
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An object is to provide a transistor including an oxide layer which includes Zn and does not include a rare metal such as In or Ga. Another object is to reduce an off current and stabilize electric characteristics in the transistor including an oxide layer which includes Zn. A transistor including an oxide layer including Zn is formed by stacking an oxide semiconductor layer including insulating oxide over an oxide layer so that the oxide layer is in contact with a source electrode layer or a drain electrode layer with the oxide semiconductor layer including insulating oxide interposed therebetween, whereby variation in the threshold voltage of the transistor can be reduced and electric characteristics can be stabilized.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide layer over the gate insulating layer;

an oxide semiconductor layer including insulating oxide over the oxide layer; and

a source electrode layer and a drain electrode layer over the oxide semiconductor layer including insulating oxide,

wherein the oxide layer and the oxide semiconductor layer including insulating oxide include Zn,

wherein the oxide layer and the oxide semiconductor layer including insulating oxide do not include indium,

wherein the oxide semiconductor layer including insulating oxide has an amorphous structure with a conductivity lower than that of the oxide layer, and

wherein the oxide semiconductor layer including insulating oxide is electrically connected to the source electrode layer and the drain electrode layer.

3. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer including insulating oxide is formed by a sputtering method using a target containing SiO₂ at 2.5 percent by weight or more and 20 percent by weight or less.

4. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer including insulating oxide is formed by a sputtering method using a target containing SiO₂ at 7.5 percent by weight or more and 12.5 percent by weight or less.

5. The semiconductor device according to claim 1,

wherein the oxide layer is an oxide semiconductor layer.

6. The semiconductor device according to claim 1,

wherein the oxide layer has a polycrystalline structure.

7. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer including insulating oxide includes a region which is between the source electrode layer and the drain electrode layer and whose thickness is smaller than that of a region overlapping with the source electrode layer or the drain electrode layer.

8. The semiconductor device according to claim 1,

wherein the gate electrode layer has a width in a channel direction which is larger than that of the oxide semiconductor layer including insulating oxide and that of the oxide layer.

9. The semiconductor device according to claim 1,

wherein a hollow is formed under an end portion of the oxide semiconductor layer including insulating oxide.

10. The semiconductor device according to claim 1,

wherein an end portion of the oxide layer is covered with the oxide semiconductor layer including insulating oxide.

11. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer including insulating oxide includes a plurality of layers,

wherein an upper layer of the plurality of layers in the oxide semiconductor layer including insulating oxide is formed by a sputtering method using a target containing a larger amount of insulating oxide than a target used to form a lower layer of the plurality of layers.

12. The semiconductor device according to claim 1,

wherein the oxide layer and the oxide semiconductor layer including insulating oxide do not include a rare metal.

13. The semiconductor device according to claim 1,

wherein the oxide layer includes only a Zn—

O-based oxide or a Sn—

Zn—

O-based oxide.

14. The semiconductor device according to claim 1,

wherein the oxide semiconductor layer including insulating oxide includes only a Zn—

O-based oxide semiconductor or a Sn—

Zn—

O-based oxide semiconductor.

15. The semiconductor device according to claim 1 further comprising:

buffer layers having n-type conductivity provided over the oxide semiconductor layer including insulating oxide so that the source electrode layer and the drain electrode layer are provided over the buffer layers,

wherein the oxide semiconductor layer including insulating oxide is electrically connected to the source electrode layer and the drain electrode layer through the buffer layers.

16. The semiconductor device according to claim 15,

wherein the buffer layers include an oxide semiconductor including Zn.

2. The semiconductor device according to claim

wherein the insulating oxide is silicon oxide.