Memory device, semiconductor device, and electronic device

• US 8,362,538 B2
• Filed: 12/22/2010
• Issued: 01/29/2013
• Est. Priority Date: 12/25/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Koyama, Jun, Yamazaki, Shunpei
• Primary Examiner(s): Lee, Hsien Ming
• Application Number:
  US12/976,206
• Publication Number:
  US 20110156024A1
• Time in Patent Office: 769 Days
• Field of Search: 438/238, 438/241, 438/258, 438/266, 257/277, 257/298, 257/300, 257/368, 257/E27.001, 257/E27.081, 257/E27.009, 257/E27.014, 326/95, 326/98, 326/119, 326/120
• US Class Current: 257/298
• CPC Class Codes: G06F 1/206 comprising thermal management
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 27/024 using a capacitive memory element G11C27/04 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H03K 19/094 using field-effect transistors
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Abstract

An object is to provide a memory device which does not need a complex manufacturing process and whose power consumption can be suppressed, and a semiconductor device including the memory device. A solution is to provide a capacitor which holds data and a switching element which controls storing and releasing charge in the capacitor in a memory element. In the memory element, a phase-inversion element such as an inverter or a clocked inverter includes the phase of an input signal is inverted and the signal is output. For the switching element, a transistor including an oxide semiconductor in a channel formation region is used. In the case where application of a power supply voltage to the phase-inversion element is stopped, the data is stored in the capacitor, so that the data is held in the capacitor even when the application of the power supply voltage to the phase-inversion element is stopped.

Claims

1. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter and a second logic element comprising at least one of an inverter and a clocked inverter, with the first and second logic elements holding data by being electrically connected to each other such that an input terminal of the first logic element is electrically connected to an output terminal of the second logic element and an input terminal of the second logic element is electrically connected to an output terminal of the first logic element;

a capacitor; and

a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor,

wherein one of a source and a drain of the transistor is electrically connected to the input terminal of the first logic element and the output terminal of the second logic element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.

6. The memory device according to any one of claims 1 to 5, wherein an OFF-state current density of the transistor is less than or equal to 100 zA/μ

m.

10. The memory device according to any one of claims 1, 2, 3, 4, 5, 7, and 8, wherein the oxide semiconductor is an In—

Ga—

Zn—

O-based oxide semiconductor.

11. The memory device according to any one of claims 1, 2, 3, 4, 5, 7, and 8, wherein an hydrogen concentration in the channel formation region is lower than or equal to 5×

10¹⁹/cm³.

12. A semiconductor device which is an LSI comprising a CPU, a DSP, or a microcontroller comprising the memory device according to any one of claims 1, 2, 3, 4, 5, 7, and 8.

13. An electronic device including a CPU including the memory device according to any one of claims 1, 2, 3, 4, 5, 7, and 8, wherein the electronic device is one selected from the group consisting of a game machine, an image reproducing device, and a personal computer.

2. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control input of a signal including data to an input terminal of the first logic element;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a capacitor; and

a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one terminal of the first switching element, the input terminal of the first logic element, and the output terminal of the second logic element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.

3. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control input of a signal including data to an input terminal of the first logic element;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a capacitor; and

a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the input terminal of the first logic element and the capacitor,

wherein one of a source and a drain of the transistor is electrically connected to one terminal of the first switching element, the input terminal of the first logic element, and the output terminal of the second logic element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.

4. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control input of a signal including data to an input terminal of the first logic element;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a third switching element which is configured to control output of a potential of the output terminal of the first logic element;

a capacitor;

a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the capacitor;

a third logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is supplied with a potential including the data written in the capacitor; and

a fourth switching element which is configured to control output of a potential of an output terminal of the third logic element,

wherein one of a source and a drain of the transistor is electrically connected to one terminal of the first switching element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.

5. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control connection between an input terminal of the first logic element and a node to which a signal including data is input;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a third switching element which is configured to control output of a potential of the output terminal of the first logic element;

a capacitor;

a transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the node and the capacitor;

a third logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is supplied with a potential including the data written in the capacitor; and

a fourth switching element which is configured to control output of a potential of an output terminal of the third logic element,

wherein one of a source and a drain of the transistor is electrically connected to one terminal of the first switching element, and the other of the source and the drain of the transistor is electrically connected to one terminal of the capacitor to write the data to the capacitor.

7. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control input of a signal including data to an input terminal of the first logic element;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a first capacitor;

a first transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the first capacitor;

a second capacitor; and

a second transistor which includes an oxide semiconductor in a channel formation region and which is configured to control writing of the data to the second capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first switching element, the input terminal of the first logic element, and the output terminal of the second logic element, and the other of the source and the drain of the first transistor is electrically connected to one terminal of the first capacitor to write the data to the first capacitor, and

wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first logic element and the input terminal of the second logic element, and the other of the source and the drain of the second transistor is electrically connected to one terminal of the second capacitor to write the data to the second capacitor.

9. The memory device according to claim 7 or claim 8, wherein an OFF-state current density of the first transistor or the second transistor is less than or equal to 100 zA/μ

m.

8. A memory device comprising a plurality of memory elements, the memory elements each comprising:

a first logic element comprising at least one of an inverter and a clocked inverter;

a second logic element comprising at least one of an inverter and a clocked inverter, an input terminal of which is electrically connected to an output terminal of the first logic element;

a first switching element which is configured to control input of a signal including data to an input terminal of the first logic element;

a second switching element which is configured to control connection between the input terminal of the first logic element and an output terminal of the second logic element;

a first capacitor;

a first transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the input terminal of the first logic element and the first capacitor;

a second capacitor; and

a second transistor which includes an oxide semiconductor in a channel formation region and which is configured to control connection between the output terminal of the first logic element and the second capacitor,

wherein one of a source and a drain of the first transistor is electrically connected to one terminal of the first switching element, the input terminal of the first logic element, and the output terminal of the second logic element, and the other of the source and the drain of the first transistor is electrically connected to one terminal of the first capacitor to write the data to the first capacitor, and

wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the first logic element and the input terminal of the second logic element, and the other of the source and the drain of the second transistor is electrically connected to one terminal of the second capacitor to write the data to the second capacitor.